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modtools: add ModIndex unit test

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This commit is contained in:
Emil J. Tywoniak 2026-02-18 22:15:44 +01:00
parent c75d80905a
commit abc7563a35
2 changed files with 56 additions and 3 deletions
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47
tests/unit/kernel/modindexTest.cc Normal file
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#include <gtest/gtest.h>
#include "kernel/modtools.h"
#include "kernel/rtlil.h"
YOSYS_NAMESPACE_BEGIN
TEST(ModIndexSwapTest, has)
{
Design* d = new Design;
Module* m = d->addModule("$m");
Wire* o = m->addWire("$o", 2);
o->port_input = true;
Wire* i = m->addWire("$i", 2);
i->port_input = true;
m->fixup_ports();
m->addNot("$not", i, o);
auto mi = ModIndex(m);
mi.reload_module();
for (auto [sb, info] : mi.database) {
EXPECT_TRUE(mi.database.find(sb) != mi.database.end());
}
m->swap_names(i, o);
for (auto [sb, info] : mi.database) {
EXPECT_TRUE(mi.database.find(sb) != mi.database.end());
}
}
TEST(ModIndexDeleteTest, has)
{
if (log_files.empty()) log_files.emplace_back(stdout);
Design* d = new Design;
Module* m = d->addModule("$m");
Wire* w = m->addWire("$w");
Wire* o = m->addWire("$o");
o->port_output = true;
m->fixup_ports();
Cell* not_ = m->addNotGate("$not", w, o);
auto mi = ModIndex(m);
mi.reload_module();
mi.dump_db();
Wire* a = m->addWire("\\a");
not_->setPort(ID::A, a);
EXPECT_TRUE(mi.ok());
}
YOSYS_NAMESPACE_END