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https://github.com/YosysHQ/yosys
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fix tests with truncation issues
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Natalia
parent
305b6c81d7
commit
d5e1647d11
1 changed files with 22 additions and 132 deletions
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@ -385,7 +385,7 @@ log -pop
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# Test 8
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log -header "Simple 1-bit ADD chain"
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log -header "Simple 1-bit ADD chain (4 inputs)"
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log -push
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design -reset
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read_verilog <<EOF
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@ -394,13 +394,13 @@ module top (
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input wire b,
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input wire c,
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input wire d,
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input wire e,
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input wire f,
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input wire g,
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input wire h,
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output wire [3:0] x,
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output wire [3:0] x
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);
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assign x = a + b + c + d + e + f + g + h;
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wire [1:0] ab;
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wire [2:0] abc;
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assign ab = a + b;
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assign abc = ab + c;
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assign x = abc + d;
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endmodule
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EOF
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check -assert
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@ -418,42 +418,20 @@ select i:a %co2 t:$add %i -set a_cell
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select i:b %co2 t:$add %i -set b_cell
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select i:c %co2 t:$add %i -set c_cell
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select i:d %co2 t:$add %i -set d_cell
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select i:e %co2 t:$add %i -set e_cell
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select i:f %co2 t:$add %i -set f_cell
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select i:g %co2 t:$add %i -set g_cell
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select i:h %co2 t:$add %i -set h_cell
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select o:x %ci2 t:$add %i -set x_cell
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select @a_cell @b_cell %i -set a_plus_b_cell
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select @c_cell @d_cell %i -set c_plus_d_cell
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select @e_cell @f_cell %i -set e_plus_f_cell
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select @g_cell @h_cell %i -set g_plus_h_cell
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select @a_cell -assert-count 1
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select @b_cell -assert-count 1
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select @c_cell -assert-count 1
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select @d_cell -assert-count 1
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select @e_cell -assert-count 1
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select @f_cell -assert-count 1
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select @g_cell -assert-count 1
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select @h_cell -assert-count 1
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select @x_cell -assert-count 1
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select @a_plus_b_cell -assert-count 1
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select @c_plus_d_cell -assert-count 1
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select @e_plus_f_cell -assert-count 1
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select @g_plus_h_cell -assert-count 1
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# Check intermediate cells
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select @a_plus_b_cell %co3 -set a_plus_b_fanout
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select @c_plus_d_cell %co3 -set c_plus_d_fanout
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select @e_plus_f_cell %co3 -set e_plus_f_fanout
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select @g_plus_h_cell %co3 -set g_plus_h_fanout
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select @a_plus_b_fanout @c_plus_d_fanout %i -set a_plus_b_plus_c_plus_d_cell
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select @e_plus_f_fanout @g_plus_h_fanout %i -set e_plus_f_plus_g_plus_h_cell
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select @a_plus_b_plus_c_plus_d_cell t:$add %i -assert-count 1
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select @e_plus_f_plus_g_plus_h_cell t:$add %i -assert-count 1
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# Check that x is ((a + b) + (c + d)) + ((e + f) + (g + h))
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select @a_plus_b_plus_c_plus_d_cell %co3 @x_cell %i -assert-count 1
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select @e_plus_f_plus_g_plus_h_cell %co3 @x_cell %i -assert-count 1
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# Check that x is (a + b) + (c + d)
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select @a_plus_b_cell %co3 @x_cell %i -assert-count 1
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select @c_plus_d_cell %co3 @x_cell %i -assert-count 1
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design -reset
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log -pop
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@ -471,8 +449,8 @@ module top (
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input wire c,
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input wire d,
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output wire [1:0] x,
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output wire [1:0] y,
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output wire [1:0] z
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output wire [2:0] y,
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output wire [3:0] z
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);
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assign x = a + b;
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assign y = x + c;
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@ -543,10 +521,10 @@ module top (
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input wire c,
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input wire d,
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output wire [1:0] x,
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output wire [1:0] y,
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output wire [1:0] z
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output wire [2:0] y,
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output wire [3:0] z
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);
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wire [1:0] temp;
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wire [2:0] temp;
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assign y = ~temp;
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assign x = a + b;
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assign temp = x + c;
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@ -615,11 +593,11 @@ module top (
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input wire b,
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input wire c,
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input wire d,
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output wire [5:0] x
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output wire [8:0] x
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);
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assign x[1:0] = a + b;
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assign x[3:2] = x[1:0] + c;
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assign x[5:4] = x[3:2] + d;
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assign x[4:2] = x[1:0] + c;
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assign x[8:5] = x[4:2] + d;
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endmodule
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EOF
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check -assert
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@ -679,14 +657,14 @@ module top (
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input wire b,
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input wire c,
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input wire d,
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output wire [5:0] x,
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output wire [8:0] x,
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output wire y
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);
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assign x[1:0] = a + b;
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assign x[3:2] = x[1:0] + c;
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assign x[5:4] = x[3:2] + d;
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assign x[4:2] = x[1:0] + c;
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assign x[8:5] = x[4:2] + d;
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assign y = x[3];
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assign y = x[4];
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endmodule
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EOF
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check -assert
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@ -736,94 +714,6 @@ log -pop
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# Test 13
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log -header "Pre-existing partial tree"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a, b, c, d,
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input wire e, f, g, h,
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input wire k, l, m, n,
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output wire [3:0] x,
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);
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wire [2:0] i, j;
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assign i = a + b + c + d;
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assign j = e + f + g + h;
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assign x = i + j + k + l + m + n;
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endmodule
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EOF
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check -assert
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# Check equivalence after opt_balance_tree
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equiv_opt -assert opt_balance_tree
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design -load postopt
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# Width reduction
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equiv_opt -assert wreduce
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design -load postopt
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# Assert that there are 11 adders
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select t:$add -assert-count 11
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# Assert that logic depth is 4
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# Check that 4 fanin-traversals results in all adders selected
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select o:x %ci2 %ci2 %ci2 %ci2 t:$add %i -assert-count 11
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design -reset
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log -pop
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# Test 14
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log -header "Pre-existing partial tree with intermediate outputs"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a, b, c, d,
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input wire e, f, g, h,
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input wire k, l, m, n,
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output wire [2:0] i, j,
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output wire [3:0] x,
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);
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assign i = a + b + c + d;
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assign j = e + f + g + h;
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assign x = i + j + k + l + m + n;
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endmodule
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EOF
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check -assert
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# Check equivalence after opt_balance_tree
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equiv_opt -assert opt_balance_tree
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design -load postopt
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# Width reduction
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equiv_opt -assert wreduce
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design -load postopt
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# Merge removes some redundancy
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equiv_opt -assert opt_merge
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design -load postopt
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# Assert that logic depth is 2 for i and j
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# Check that 2 fanin-traversals results in all adders selected
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select o:i %ci2 %ci2 t:$add %i -assert-count 3
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select o:j %ci2 %ci2 t:$add %i -assert-count 3
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# Assert that logic depth is 4 for x
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# Check that 4 fanin-traversals results in 11 adders selected
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select o:x %ci2 %ci2 %ci2 %ci2 t:$add %i -assert-count 11
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design -reset
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log -pop
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# Test 15
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log -header "Mixed signed/unsigned adders with different bit widths"
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log -push
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