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opt_expr: fix const lhs of $pow to $shl
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2 changed files with 61 additions and 2 deletions
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@ -1667,7 +1667,11 @@ skip_identity:
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int bit_idx;
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const auto onehot = sig_a.is_onehot(&bit_idx);
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if (onehot) {
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// Power of two
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// A is unsigned or positive
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if (onehot && (!cell->parameters[ID::A_SIGNED].as_bool() || bit_idx < sig_a.size() - 1)) {
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cell->parameters[ID::A_SIGNED] = 0;
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// 2^B = 1<<B
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if (bit_idx == 1) {
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log_debug("Replacing pow cell `%s' in module `%s' with left-shift\n",
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cell->name.c_str(), module->name.c_str());
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@ -1679,7 +1683,6 @@ skip_identity:
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log_debug("Replacing pow cell `%s' in module `%s' with multiply and left-shift\n",
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cell->name.c_str(), module->name.c_str());
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cell->type = ID($mul);
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cell->parameters[ID::A_SIGNED] = 0;
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cell->setPort(ID::A, Const(bit_idx, cell->parameters[ID::A_WIDTH].as_int()));
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SigSpec y_wire = module->addWire(NEW_ID, y_size);
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@ -319,3 +319,59 @@ check
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equiv_opt -assert opt_expr -keepdc
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design -load postopt
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select -assert-count 1 t:$mul r:A_WIDTH=4 %i r:B_WIDTH=4 %i r:Y_WIDTH=8 %i
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###########
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design -reset
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read_rtlil <<EOF
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module \top
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wire width 3 input 2 \binary
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wire width 32 output 3 \y
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cell $pow $0
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parameter \A_WIDTH 32
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parameter \B_WIDTH 3
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parameter \A_SIGNED 1
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parameter \B_SIGNED 0
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parameter \Y_WIDTH 32
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connect \A 2
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connect \B \binary
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connect \Y \y
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end
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end
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EOF
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scratchpad -set opt.did_something false
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opt_expr
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scratchpad -assert opt.did_something true
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sat -verify -set binary 0 -prove y 1
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sat -verify -set binary 1 -prove y 2
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sat -verify -set binary 2 -prove y 4
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sat -verify -set binary 3 -prove y 8
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###########
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design -reset
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read_rtlil <<EOF
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module \top
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wire width 3 input 2 \binary
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wire width 32 output 3 \y
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cell $pow $0
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parameter \A_WIDTH 2
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parameter \B_WIDTH 3
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parameter \A_SIGNED 1
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parameter \B_SIGNED 0
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parameter \Y_WIDTH 32
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connect \A 2'10
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connect \B \binary
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connect \Y \y
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end
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end
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EOF
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scratchpad -set opt.did_something false
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opt_expr
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scratchpad -assert opt.did_something false
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