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modify generator for pyosys/wrappers.cc instead of headers

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This commit is contained in:
Natalia 2026-01-18 02:11:09 -08:00
parent fb864e91ee
commit cf511628b0
5 changed files with 22 additions and 68 deletions
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7
kernel/rtlil.cc
View file

@ -1610,13 +1610,6 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_modules(RTLIL::SelectPartial
return result;
}
void RTLIL::Design::run_pass(std::string command)
{
log("\n-- Running command `%s' --\n", command.c_str());
Pass::call(this, command);
log_flush();
}
RTLIL::Module::Module()
{
static unsigned int hashidx_count = 123456789;

2
kernel/rtlil.h
View file

@ -2032,8 +2032,6 @@ struct RTLIL::Design
// partially selected or boxed modules have been ignored
std::vector<RTLIL::Module*> selected_unboxed_whole_modules_warn() const { return selected_modules(SELECT_WHOLE_WARN, SB_UNBOXED_WARN); }
void run_pass(std::string command);
static std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);
std::string to_rtlil_str(bool only_selected = true) const;

10
pyosys/generator.py
View file

@ -701,6 +701,16 @@ class PyosysWrapperGenerator(object):
self.process_class_members(metadata, metadata, cls, basename)
if basename == "Design":
print(
'\t\t\t.def("run_pass", [](Design &s, std::vector<std::string> cmd) { Pass::call(cmd, &s); })',
file=self.f,
)
print(
'\t\t\t.def("run_pass", [](Design &s, std::string cmd) { Pass::call(cmd, &s); })',
file=self.f,
)
if expr := metadata.string_expr:
print(
f'\t\t.def("__str__", [](const {basename} &s) {{ return {expr}; }})',

12
tests/pyosys/test_design_run_pass.py Normal file
View file

@ -0,0 +1,12 @@
from pathlib import Path
from pyosys import libyosys as ys
__file_dir__ = Path(__file__).absolute().parent
design = ys.Design()
design.run_pass(
["read_verilog", str(__file_dir__.parent / "simple" / "fiedler-cooley.v")]
)
design.run_pass("prep")
design.run_pass(["opt", "-full"])

59
tests/unit/kernel/test_design_run_pass.cc
View file

@ -1,59 +0,0 @@
#include <gtest/gtest.h>
#include "kernel/rtlil.h"
#include "kernel/register.h"
YOSYS_NAMESPACE_BEGIN
class DesignRunPassTest : public testing::Test {
protected:
DesignRunPassTest() {
if (log_files.empty()) log_files.emplace_back(stdout);
}
virtual void SetUp() override {
IdString::ensure_prepopulated();
}
};
TEST_F(DesignRunPassTest, RunPassExecutesSuccessfully)
{
// Create a design with a simple module
RTLIL::Design *design = new RTLIL::Design;
RTLIL::Module *module = new RTLIL::Module;
module->name = RTLIL::IdString("\\test_module");
design->add(module);
// Add a simple wire to the module
RTLIL::Wire *wire = module->addWire(RTLIL::IdString("\\test_wire"), 1);
wire->port_input = true;
wire->port_id = 1;
module->fixup_ports();
// Call run_pass with a simple pass
// We use "check" which is a simple pass that just validates the design
ASSERT_NO_THROW(design->run_pass("check"));
// Verify the design still exists and has the module
EXPECT_EQ(design->modules().size(), 1);
EXPECT_NE(design->module(RTLIL::IdString("\\test_module")), nullptr);
delete design;
}
TEST_F(DesignRunPassTest, RunPassWithHierarchy)
{
// Create a design with a simple module
RTLIL::Design *design = new RTLIL::Design;
RTLIL::Module *module = new RTLIL::Module;
module->name = RTLIL::IdString("\\top");
design->add(module);
// Call run_pass with hierarchy pass
ASSERT_NO_THROW(design->run_pass("hierarchy"));
// Verify the design still has the module
EXPECT_EQ(design->modules().size(), 1);
delete design;
}
YOSYS_NAMESPACE_END