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https://github.com/YosysHQ/yosys
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modify generator for pyosys/wrappers.cc instead of headers
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5 changed files with 22 additions and 68 deletions
12
tests/pyosys/test_design_run_pass.py
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12
tests/pyosys/test_design_run_pass.py
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from pathlib import Path
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from pyosys import libyosys as ys
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__file_dir__ = Path(__file__).absolute().parent
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design = ys.Design()
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design.run_pass(
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["read_verilog", str(__file_dir__.parent / "simple" / "fiedler-cooley.v")]
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)
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design.run_pass("prep")
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design.run_pass(["opt", "-full"])
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@ -1,59 +0,0 @@
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#include <gtest/gtest.h>
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#include "kernel/rtlil.h"
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#include "kernel/register.h"
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YOSYS_NAMESPACE_BEGIN
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class DesignRunPassTest : public testing::Test {
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protected:
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DesignRunPassTest() {
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if (log_files.empty()) log_files.emplace_back(stdout);
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}
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virtual void SetUp() override {
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IdString::ensure_prepopulated();
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}
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};
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TEST_F(DesignRunPassTest, RunPassExecutesSuccessfully)
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{
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// Create a design with a simple module
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RTLIL::Design *design = new RTLIL::Design;
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RTLIL::Module *module = new RTLIL::Module;
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module->name = RTLIL::IdString("\\test_module");
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design->add(module);
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// Add a simple wire to the module
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RTLIL::Wire *wire = module->addWire(RTLIL::IdString("\\test_wire"), 1);
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wire->port_input = true;
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wire->port_id = 1;
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module->fixup_ports();
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// Call run_pass with a simple pass
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// We use "check" which is a simple pass that just validates the design
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ASSERT_NO_THROW(design->run_pass("check"));
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// Verify the design still exists and has the module
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EXPECT_EQ(design->modules().size(), 1);
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EXPECT_NE(design->module(RTLIL::IdString("\\test_module")), nullptr);
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delete design;
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}
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TEST_F(DesignRunPassTest, RunPassWithHierarchy)
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{
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// Create a design with a simple module
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RTLIL::Design *design = new RTLIL::Design;
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RTLIL::Module *module = new RTLIL::Module;
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module->name = RTLIL::IdString("\\top");
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design->add(module);
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// Call run_pass with hierarchy pass
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ASSERT_NO_THROW(design->run_pass("hierarchy"));
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// Verify the design still has the module
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EXPECT_EQ(design->modules().size(), 1);
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delete design;
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}
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YOSYS_NAMESPACE_END
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