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use run_pass in ecp5 add/sub test

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Natalia 2026-01-29 02:42:23 -08:00
parent 7439d2489e
commit 61b1c3c75a
1 changed files with 16 additions and 9 deletions
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25
tests/pyosys/test_design_run_pass.py
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@ -1,13 +1,20 @@
from pathlib import Path
from pathlib import Path
from pyosys import libyosys as ys
__file_dir__ = Path(__file__).absolute().parent
src = __file_dir__.parent / "simple" / "fiedler-cooley.v"
add_sub = __file_dir__.parent / "arch" / "common" / "add_sub.v"
design = ys.Design()
design.run_pass(["read_verilog", str(src)])
design.run_pass("hierarchy -top up3down5")
design.run_pass(["proc"])
design.run_pass("opt -full")
design.run_pass("select -assert-mod-count 1 up3down5")
base = ys.Design()
base.run_pass(["read_verilog", str(add_sub)])
base.run_pass("hierarchy -top top")
base.run_pass(["proc"])
base.run_pass("equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5")
postopt = ys.Design()
postopt.run_pass("design -load postopt")
postopt.run_pass(["cd", "top"])
postopt.run_pass("select -assert-min 25 t:LUT4")
postopt.run_pass("select -assert-max 26 t:LUT4")
postopt.run_pass(["select", "-assert-count", "10", "t:PFUMX"])
postopt.run_pass(["select", "-assert-count", "6", "t:L6MUX21"])
postopt.run_pass("select -assert-none t:LUT4 t:PFUMX t:L6MUX21 %% t:* %D")