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Merge pull request #4269 from povik/icells_not_derived

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Avoid `module_not_derived` on internal cells in techmap result
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Gus Smith 2026-01-26 14:48:40 -08:00 • committed by GitHub
commit 09ceadfde7
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3 changed files with 42 additions and 27 deletions
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7
frontends/ast/genrtlil.cc
View file

@ -2085,8 +2085,6 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
check_unique_id(current_module, id, this, "cell");
RTLIL::Cell *cell = current_module->addCell(id, "");
set_src_attr(cell, this);
// Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass
cell->set_bool_attribute(ID::module_not_derived);
for (auto it = children.begin(); it != children.end(); it++) {
auto* child = it->get();
@ -2149,6 +2147,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
}
log_abort();
}
// Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass
if (cell->type.isPublic())
cell->set_bool_attribute(ID::module_not_derived);
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)
input_error("Attribute `%s' with non-constant value.\n", attr.first);

31
passes/techmap/techmap.cc
View file

@ -333,9 +333,6 @@ struct TechmapWorker
RTLIL::Cell *c = module->addCell(c_name, tpl_cell);
design->select(module, c);
if (c->type.begins_with("\\$"))
c->type = c->type.substr(1);
if (c->type == ID::_TECHMAP_PLACEHOLDER_ && tpl_cell->has_attribute(ID::techmap_chtype)) {
c->type = RTLIL::escape_id(tpl_cell->get_string_attribute(ID::techmap_chtype));
@ -436,13 +433,9 @@ struct TechmapWorker
if (handled_cells.count(cell) > 0)
continue;
std::string cell_type = cell->type.str();
if (in_recursion && cell->type.begins_with("\\$"))
cell_type = cell_type.substr(1);
if (celltypeMap.count(cell_type) == 0) {
if (assert_mode && cell_type.back() != '_')
log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell_type));
if (celltypeMap.count(cell->type) == 0) {
if (assert_mode && !cell->type.ends_with("_"))
log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell->type));
continue;
}
@ -454,7 +447,7 @@ struct TechmapWorker
if (GetSize(sig) == 0)
continue;
for (auto &tpl_name : celltypeMap.at(cell_type)) {
for (auto &tpl_name : celltypeMap.at(cell->type)) {
RTLIL::Module *tpl = map->module(tpl_name);
RTLIL::Wire *port = tpl->wire(conn.first);
if (port && port->port_input)
@ -481,12 +474,7 @@ struct TechmapWorker
log_assert(cell == module->cell(cell->name));
bool mapped_cell = false;
std::string cell_type = cell->type.str();
if (in_recursion && cell->type.begins_with("\\$"))
cell_type = cell_type.substr(1);
for (auto &tpl_name : celltypeMap.at(cell_type))
for (auto &tpl_name : celltypeMap.at(cell->type))
{
IdString derived_name = tpl_name;
RTLIL::Module *tpl = map->module(tpl_name);
@ -508,8 +496,6 @@ struct TechmapWorker
if (!extmapper_name.empty())
{
cell->type = cell_type;
if ((extern_mode && !in_recursion) || extmapper_name == "wrap")
{
std::string m_name = stringf("$extern:%s:%s", extmapper_name, log_id(cell->type));
@ -935,11 +921,6 @@ struct TechmapWorker
RTLIL::Module *m = design->addModule(m_name);
tpl->cloneInto(m);
for (auto cell : m->cells()) {
if (cell->type.begins_with("\\$"))
cell->type = cell->type.substr(1);
}
module_queue.insert(m);
}
@ -1168,7 +1149,7 @@ struct TechmapPass : public Pass {
std::vector<std::string> map_files;
std::vector<RTLIL::IdString> dont_map;
std::string verilog_frontend = "verilog -nooverwrite -noblackbox";
std::string verilog_frontend = "verilog -nooverwrite -noblackbox -icells";
int max_iter = -1;
size_t argidx;

31
tests/techmap/module_not_derived.ys Normal file
View file

@ -0,0 +1,31 @@
# Test 1: internal cells from alumacc/techmap must not keep module_not_derived.
read_verilog <<EOF_VERILOG
module top(a, b, y);
input wire [7:0] a;
input wire [7:0] b;
output wire [7:0] y;
assign y = a + b;
endmodule
EOF_VERILOG
prep
alumacc
techmap -max_iter 1
select -assert-any t:$lcu
select -assert-count 0 t:$lcu a:module_not_derived %i
design -reset
# Test 2: public module instances should still keep module_not_derived.
read_verilog <<EOF_VERILOG
module mycell(input a, output y);
assign y = a;
endmodule
module top(input a, output y);
mycell u0(.a(a), .y(y));
endmodule
EOF_VERILOG
hierarchy -top top
select -assert-any t:mycell a:module_not_derived %i