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Consolidated hana test benches into fewer files

Browse source 
for pf in test_simulation_{always,and,buffer,decoder,inc,mux,nand,nor,or,seq,shifter,sop,techmap,xnor,xor}; do
gawk 'FNR == 1 { printf("\n// %s\n",FILENAME); } { gsub("^module *", sprintf("module f%d_",ARGIND)); print; }' \
    ${pf}_*_test.v > $pf.v; ../tools/autotest.sh $pf.v; mv -v ${pf}_*_test.v Attic/; done;

..etc..
This commit is contained in:
Clifford Wolf 2014-08-01 03:57:37 +02:00
parent 03ef9a75c6
commit 5e641acc90
175 changed files with 1622 additions and 1332 deletions
Download patch file Download diff file Expand all files Collapse all files

10
tests/hana/README
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@ -2,13 +2,3 @@
This test cases are copied from the hana project:
https://sourceforge.net/projects/sim-sim/
** Copy tests from hana: **
while read fn; do cp -v $fn ALL_TESTS/${fn//\//_}; done < <(find test -name '*.v' ! -name '*_gold.v')
** Eliminate test's we can't parse atm: **
rm -f test_synthesizability*.v
rm -f test_parse2synthtrans_latch_1_test.v
rm -f test_parse2synthtrans_always_1_test.v
rm -f test_parse2synthtrans_always_2_test.v
for x in test_*.v; do ../../yosys -b "" $x || rm $x; done

2
tests/hana/run-test.sh
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@ -1,2 +1,2 @@
#!/bin/bash
exec ${MAKE:-make} -f ../tools/autotest.mk EXTRA_FLAGS="-l hana_vlib.v" test_*.v
exec ${MAKE:-make} -f ../tools/autotest.mk EXTRA_FLAGS="-l hana_vlib.v -n 300" test_*.v

418
tests/hana/test_intermout.v Normal file
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// test_intermout_always_comb_1_test.v
module f1_test(a, b, c, d, z);
input a, b, c, d;
output z;
reg z, temp1, temp2;
always @(a or b or c or d)
begin
temp1 = a ^ b;
temp2 = c ^ d;
z = temp1 ^ temp2;
end
endmodule
// test_intermout_always_comb_3_test.v
module f2_test (in1, in2, out);
input in1, in2;
output reg out;
always @ ( in1 or in2)
if(in1 > in2)
out = in1;
else
out = in2;
endmodule
// test_intermout_always_comb_4_test.v
module f3_test(a, b, c);
input b, c;
output reg a;
always @(b or c) begin
a = b;
a = c;
end
endmodule
// test_intermout_always_comb_5_test.v
module f4_test(ctrl, in1, in2, out);
input ctrl;
input in1, in2;
output reg out;
always @ (ctrl or in1 or in2)
if(ctrl)
out = in1 & in2;
else
out = in1 | in2;
endmodule
// test_intermout_always_ff_3_test.v
module f5_NonBlockingEx(clk, merge, er, xmit, fddi, claim);
input clk, merge, er, xmit, fddi;
output reg claim;
reg fcr;
always @(posedge clk)
begin
fcr = er | xmit;
if(merge)
claim = fcr & fddi;
else
claim = fddi;
end
endmodule
// test_intermout_always_ff_4_test.v
module f6_FlipFlop(clk, cs, ns);
input clk;
input [31:0] cs;
output [31:0] ns;
integer is;
always @(posedge clk)
is <= cs;
assign ns = is;
endmodule
// test_intermout_always_ff_5_test.v
module f7_FlipFlop(clock, cs, ns);
input clock;
input [3:0] cs;
output reg [3:0] ns;
reg [3:0] temp;
always @(posedge clock)
begin
temp = cs;
ns = temp;
end
endmodule
// test_intermout_always_ff_6_test.v
module f8_inc(clock, counter);
input clock;
output reg [3:0] counter;
always @(posedge clock)
counter <= counter + 1;
endmodule
// test_intermout_always_ff_8_test.v
module f9_NegEdgeClock(q, d, clk, reset);
input d, clk, reset;
output reg q;
always @(negedge clk or negedge reset)
if(!reset)
q <= 1'b0;
else
q <= d;
endmodule
// test_intermout_always_ff_9_test.v
module f10_MyCounter (clock, preset, updown, presetdata, counter);
input clock, preset, updown;
input [1: 0] presetdata;
output reg [1:0] counter;
always @(posedge clock)
if(preset)
counter <= presetdata;
else
if(updown)
counter <= counter + 1;
else
counter <= counter - 1;
endmodule
// test_intermout_always_latch_1_test.v
module f11_test(en, in, out);
input en;
input [1:0] in;
output reg [2:0] out;
always @ (en or in)
if(en)
out = in + 1;
endmodule
// test_intermout_bufrm_1_test.v
module f12_test(input in, output out);
//no buffer removal
assign out = in;
endmodule
// test_intermout_bufrm_2_test.v
module f13_test(input in, output out);
//intermediate buffers should be removed
wire w1, w2;
assign w1 = in;
assign w2 = w1;
assign out = w2;
endmodule
// test_intermout_bufrm_6_test.v
module f14_test(in, out);
input in;
output out;
wire w1, w2, w3, w4;
assign w1 = in;
assign w2 = w1;
assign w4 = w3;
assign out = w4;
f14_mybuf _f14_mybuf(w2, w3);
endmodule
module f14_mybuf(in, out);
input in;
output out;
wire w1, w2, w3, w4;
assign w1 = in;
assign w2 = w1;
assign out = w2;
endmodule
// test_intermout_bufrm_7_test.v
module f15_test(in1, in2, out);
input in1, in2;
output out;
// Y with cluster of f15_mybuf instances at the junction
wire w1, w2, w3, w4, w5, w6, w7, w8, w9, w10;
assign w1 = in1;
assign w2 = w1;
assign w5 = in2;
assign w6 = w5;
assign w10 = w9;
assign out = w10;
f15_mybuf _f15_mybuf0(w2, w3);
f15_mybuf _f15_mybuf1(w3, w4);
f15_mybuf _f15_mybuf2(w6, w7);
f15_mybuf _f15_mybuf3(w7, w4);
f15_mybuf _f15_mybuf4(w4, w8);
f15_mybuf _f15_mybuf5(w8, w9);
endmodule
module f15_mybuf(in, out);
input in;
output out;
wire w1, w2, w3, w4;
assign w1 = in;
assign w2 = w1;
assign out = w2;
endmodule
// test_intermout_exprs_add_test.v
module f16_test(out, in1, in2, vin1, vin2, vout1);
output out;
input in1, in2;
input [1:0] vin1;
input [2:0] vin2;
output [3:0] vout1;
assign out = in1 + in2;
assign vout1 = vin1 + vin2;
endmodule
// test_intermout_exprs_binlogic_test.v
module f17_test(in1, in2, vin1, vin2, out, vout, vin3, vin4, vout1 );
input in1, in2;
input [1:0] vin1;
input [3:0] vin2;
input [1:0] vin3;
input [3:0] vin4;
output vout, vout1;
output out;
assign out = in1 && in2;
assign vout = vin1 && vin2;
assign vout1 = vin3 || vin4;
endmodule
// test_intermout_exprs_bitwiseneg_test.v
module f18_test(output out, input in, output [1:0] vout, input [1:0] vin);
assign out = ~in;
assign vout = ~vin;
endmodule
// test_intermout_exprs_buffer_test.v
module f19_buffer(in, out, vin, vout);
input in;
output out;
input [1:0] vin;
output [1:0] vout;
assign out = in;
assign vout = vin;
endmodule
// test_intermout_exprs_condexpr_mux_test.v
module f20_test(in1, in2, out, vin1, vin2, vin3, vin4, vout1, vout2, en1, ven1, ven2);
input in1, in2, en1, ven1;
input [1:0] ven2;
output out;
input [1:0] vin1, vin2, vin3, vin4;
output [1:0] vout1, vout2;
assign out = en1 ? in1 : in2;
assign vout1 = ven1 ? vin1 : vin2;
assign vout2 = ven2 ? vin3 : vin4;
endmodule
// test_intermout_exprs_condexpr_tribuf_test.v
module f21_test(in, out, en, vin1, vout1, en1);
input in, en, en1;
output out;
input [1:0] vin1;
output [1:0] vout1;
assign out = en ? in : 1'bz;
assign vout1 = en1 ? vin1 : 2'bzz;
endmodule
// test_intermout_exprs_constshift_test.v
module f22_test(in, out, vin, vout, vin1, vout1, vin2, vout2);
input in;
input [3:0] vin, vin1, vin2;
output [3:0] vout, vout1, vout2;
output out;
assign out = in << 1;
assign vout = vin << 2;
assign vout1 = vin1 >> 2;
assign vout2 = vin2 >>> 2;
endmodule
// test_intermout_exprs_const_test.v
module f23_test (out, vout);
output out;
output [7:0] vout;
assign out = 1'b1;
assign vout = 9;
endmodule
// test_intermout_exprs_div_test.v
module f24_test(out, in1, in2, vin1, vin2, vout1);
output out;
input in1, in2;
input [1:0] vin1;
input [2:0] vin2;
output [3:0] vout1;
assign out = in1 / in2;
assign vout1 = vin1 / vin2;
endmodule
// test_intermout_exprs_logicneg_test.v
module f25_test(out, vout, in, vin);
output out, vout;
input in;
input [3:0] vin;
assign out = !in;
assign vout = !vin;
endmodule
// test_intermout_exprs_mod_test.v
module f26_test(out, in1, in2, vin1, vin2, vout1);
output out;
input in1, in2;
input [1:0] vin1;
input [2:0] vin2;
output [3:0] vout1;
assign out = in1 % in2;
assign vout1 = vin1 % vin2;
endmodule
// test_intermout_exprs_mul_test.v
module f27_test(out, in1, in2, vin1, vin2, vout1);
output out;
input in1, in2;
input [1:0] vin1;
input [2:0] vin2;
output [3:0] vout1;
assign out = in1 * in2;
assign vout1 = vin1 * vin2;
endmodule
// test_intermout_exprs_redand_test.v
module f28_test(output out, input [1:0] vin, output out1, input [3:0] vin1);
assign out = &vin;
assign out1 = &vin1;
endmodule
// test_intermout_exprs_redop_test.v
module f29_Reduction (A1, A2, A3, A4, A5, A6, Y1, Y2, Y3, Y4, Y5, Y6);
input [1:0] A1;
input [1:0] A2;
input [1:0] A3;
input [1:0] A4;
input [1:0] A5;
input [1:0] A6;
output Y1, Y2, Y3, Y4, Y5, Y6;
//reg Y1, Y2, Y3, Y4, Y5, Y6;
assign Y1=&A1; //reduction AND
assign Y2=|A2; //reduction OR
assign Y3=~&A3; //reduction NAND
assign Y4=~|A4; //reduction NOR
assign Y5=^A5; //reduction XOR
assign Y6=~^A6; //reduction XNOR
endmodule
// test_intermout_exprs_sub_test.v
module f30_test(out, in1, in2, vin1, vin2, vout1);
output out;
input in1, in2;
input [1:0] vin1;
input [2:0] vin2;
output [3:0] vout1;
assign out = in1 - in2;
assign vout1 = vin1 - vin2;
endmodule
// test_intermout_exprs_unaryminus_test.v
module f31_test(output out, input in, output [31:0] vout, input [31:0] vin);
assign out = -in;
assign vout = -vin;
endmodule
// test_intermout_exprs_unaryplus_test.v
module f32_test(output out, input in);
assign out = +in;
endmodule
// test_intermout_exprs_varshift_test.v
module f33_test(vin0, vout0);
input [2:0] vin0;
output reg [7:0] vout0;
wire [7:0] myreg0, myreg1, myreg2;
integer i;
assign myreg0 = vout0 << vin0;
assign myreg1 = myreg2 >> i;
endmodule

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tests/hana/test_intermout_always_comb_1_test.v
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@ -1,13 +0,0 @@
module test(a, b, c, d, z);
input a, b, c, d;
output z;
reg z, temp1, temp2;
always @(a or b or c or d)
begin
temp1 = a ^ b;
temp2 = c ^ d;
z = temp1 ^ temp2;
end
endmodule

10
tests/hana/test_intermout_always_comb_3_test.v
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@ -1,10 +0,0 @@
module test (in1, in2, out);
input in1, in2;
output reg out;
always @ ( in1 or in2)
if(in1 > in2)
out = in1;
else
out = in2;
endmodule

9
tests/hana/test_intermout_always_comb_4_test.v
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@ -1,9 +0,0 @@
module test(a, b, c);
input b, c;
output reg a;
always @(b or c) begin
a = b;
a = c;
end
endmodule

11
tests/hana/test_intermout_always_comb_5_test.v
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@ -1,11 +0,0 @@
module test(ctrl, in1, in2, out);
input ctrl;
input in1, in2;
output reg out;
always @ (ctrl or in1 or in2)
if(ctrl)
out = in1 & in2;
else
out = in1 | in2;
endmodule

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tests/hana/test_intermout_always_ff_3_test.v
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@ -1,15 +0,0 @@
module NonBlockingEx(clk, merge, er, xmit, fddi, claim);
input clk, merge, er, xmit, fddi;
output reg claim;
reg fcr;
always @(posedge clk)
begin
fcr = er | xmit;
if(merge)
claim = fcr & fddi;
else
claim = fddi;
end
endmodule

11
tests/hana/test_intermout_always_ff_4_test.v
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@ -1,11 +0,0 @@
module FlipFlop(clk, cs, ns);
input clk;
input [31:0] cs;
output [31:0] ns;
integer is;
always @(posedge clk)
is <= cs;
assign ns = is;
endmodule

13
tests/hana/test_intermout_always_ff_5_test.v
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@ -1,13 +0,0 @@
module FlipFlop(clock, cs, ns);
input clock;
input [3:0] cs;
output reg [3:0] ns;
reg [3:0] temp;
always @(posedge clock)
begin
temp = cs;
ns = temp;
end
endmodule

7
tests/hana/test_intermout_always_ff_6_test.v
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@ -1,7 +0,0 @@
module inc(clock, counter);
input clock;
output reg [3:0] counter;
always @(posedge clock)
counter <= counter + 1;
endmodule

11
tests/hana/test_intermout_always_ff_8_test.v
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@ -1,11 +0,0 @@
module NegEdgeClock(q, d, clk, reset);
input d, clk, reset;
output reg q;
always @(negedge clk or negedge reset)
if(!reset)
q <= 1'b0;
else
q <= d;
endmodule

14
tests/hana/test_intermout_always_ff_9_test.v
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@ -1,14 +0,0 @@
module MyCounter (clock, preset, updown, presetdata, counter);
input clock, preset, updown;
input [1: 0] presetdata;
output reg [1:0] counter;
always @(posedge clock)
if(preset)
counter <= presetdata;
else
if(updown)
counter <= counter + 1;
else
counter <= counter - 1;
endmodule

9
tests/hana/test_intermout_always_latch_1_test.v
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@ -1,9 +0,0 @@
module test(en, in, out);
input en;
input [1:0] in;
output reg [2:0] out;
always @ (en or in)
if(en)
out = in + 1;
endmodule

4
tests/hana/test_intermout_bufrm_1_test.v
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@ -1,4 +0,0 @@
module test(input in, output out);
//no buffer removal
assign out = in;
endmodule

7
tests/hana/test_intermout_bufrm_2_test.v
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@ -1,7 +0,0 @@
module test(input in, output out);
//intermediate buffers should be removed
wire w1, w2;
assign w1 = in;
assign w2 = w1;
assign out = w2;
endmodule

22
tests/hana/test_intermout_bufrm_6_test.v
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@ -1,22 +0,0 @@
module test(in, out);
input in;
output out;
wire w1, w2, w3, w4;
assign w1 = in;
assign w2 = w1;
assign w4 = w3;
assign out = w4;
mybuf _mybuf(w2, w3);
endmodule
module mybuf(in, out);
input in;
output out;
wire w1, w2, w3, w4;
assign w1 = in;
assign w2 = w1;
assign out = w2;
endmodule

33
tests/hana/test_intermout_bufrm_7_test.v
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@ -1,33 +0,0 @@
module test(in1, in2, out);
input in1, in2;
output out;
// Y with cluster of mybuf instances at the junction
wire w1, w2, w3, w4, w5, w6, w7, w8, w9, w10;
assign w1 = in1;
assign w2 = w1;
assign w5 = in2;
assign w6 = w5;
assign w10 = w9;
assign out = w10;
mybuf _mybuf0(w2, w3);
mybuf _mybuf1(w3, w4);
mybuf _mybuf2(w6, w7);
mybuf _mybuf3(w7, w4);
mybuf _mybuf4(w4, w8);
mybuf _mybuf5(w8, w9);
endmodule
module mybuf(in, out);
input in;
output out;
wire w1, w2, w3, w4;
assign w1 = in;
assign w2 = w1;
assign out = w2;
endmodule

10
tests/hana/test_intermout_exprs_add_test.v
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@ -1,10 +0,0 @@
module test(out, in1, in2, vin1, vin2, vout1);
output out;
input in1, in2;
input [1:0] vin1;
input [2:0] vin2;
output [3:0] vout1;
assign out = in1 + in2;
assign vout1 = vin1 + vin2;
endmodule

13
tests/hana/test_intermout_exprs_binlogic_test.v
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@ -1,13 +0,0 @@
module test(in1, in2, vin1, vin2, out, vout, vin3, vin4, vout1 );
input in1, in2;
input [1:0] vin1;
input [3:0] vin2;
input [1:0] vin3;
input [3:0] vin4;
output vout, vout1;
output out;
assign out = in1 && in2;
assign vout = vin1 && vin2;
assign vout1 = vin3 || vin4;
endmodule

5
tests/hana/test_intermout_exprs_bitwiseneg_test.v
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@ -1,5 +0,0 @@
module test(output out, input in, output [1:0] vout, input [1:0] vin);
assign out = ~in;
assign vout = ~vin;
endmodule

9
tests/hana/test_intermout_exprs_buffer_test.v
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@ -1,9 +0,0 @@
module buffer(in, out, vin, vout);
input in;
output out;
input [1:0] vin;
output [1:0] vout;
assign out = in;
assign vout = vin;
endmodule

11
tests/hana/test_intermout_exprs_condexpr_mux_test.v
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@ -1,11 +0,0 @@
module test(in1, in2, out, vin1, vin2, vin3, vin4, vout1, vout2, en1, ven1, ven2);
input in1, in2, en1, ven1;
input [1:0] ven2;
output out;
input [1:0] vin1, vin2, vin3, vin4;
output [1:0] vout1, vout2;
assign out = en1 ? in1 : in2;
assign vout1 = ven1 ? vin1 : vin2;
assign vout2 = ven2 ? vin3 : vin4;
endmodule

9
tests/hana/test_intermout_exprs_condexpr_tribuf_test.v
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@ -1,9 +0,0 @@
module test(in, out, en, vin1, vout1, en1);
input in, en, en1;
output out;
input [1:0] vin1;
output [1:0] vout1;
assign out = en ? in : 1'bz;
assign vout1 = en1 ? vin1 : 2'bzz;
endmodule

7
tests/hana/test_intermout_exprs_const_test.v
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@ -1,7 +0,0 @@
module test (out, vout);
output out;
output [7:0] vout;
assign out = 1'b1;
assign vout = 9;
endmodule

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tests/hana/test_intermout_exprs_constshift_test.v
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@ -1,12 +0,0 @@
module test(in, out, vin, vout, vin1, vout1, vin2, vout2);
input in;
input [3:0] vin, vin1, vin2;
output [3:0] vout, vout1, vout2;
output out;
assign out = in << 1;
assign vout = vin << 2;
assign vout1 = vin1 >> 2;
assign vout2 = vin2 >>> 2;
endmodule

10
tests/hana/test_intermout_exprs_div_test.v
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@ -1,10 +0,0 @@
module test(out, in1, in2, vin1, vin2, vout1);
output out;
input in1, in2;
input [1:0] vin1;
input [2:0] vin2;
output [3:0] vout1;
assign out = in1 / in2;
assign vout1 = vin1 / vin2;
endmodule

7
tests/hana/test_intermout_exprs_logicneg_test.v
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@ -1,7 +0,0 @@
module test(out, vout, in, vin);
output out, vout;
input in;
input [3:0] vin;
assign out = !in;
assign vout = !vin;
endmodule

10
tests/hana/test_intermout_exprs_mod_test.v
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@ -1,10 +0,0 @@
module test(out, in1, in2, vin1, vin2, vout1);
output out;
input in1, in2;
input [1:0] vin1;
input [2:0] vin2;
output [3:0] vout1;
assign out = in1 % in2;
assign vout1 = vin1 % vin2;
endmodule

10
tests/hana/test_intermout_exprs_mul_test.v
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@ -1,10 +0,0 @@
module test(out, in1, in2, vin1, vin2, vout1);
output out;
input in1, in2;
input [1:0] vin1;
input [2:0] vin2;
output [3:0] vout1;
assign out = in1 * in2;
assign vout1 = vin1 * vin2;
endmodule

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tests/hana/test_intermout_exprs_redand_test.v
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@ -1,5 +0,0 @@
module test(output out, input [1:0] vin, output out1, input [3:0] vin1);
assign out = &vin;
assign out1 = &vin1;
endmodule

16
tests/hana/test_intermout_exprs_redop_test.v
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module Reduction (A1, A2, A3, A4, A5, A6, Y1, Y2, Y3, Y4, Y5, Y6);
input [1:0] A1;
input [1:0] A2;
input [1:0] A3;
input [1:0] A4;
input [1:0] A5;
input [1:0] A6;
output Y1, Y2, Y3, Y4, Y5, Y6;
//reg Y1, Y2, Y3, Y4, Y5, Y6;
assign Y1=&A1; //reduction AND
assign Y2=|A2; //reduction OR
assign Y3=~&A3; //reduction NAND
assign Y4=~|A4; //reduction NOR
assign Y5=^A5; //reduction XOR
assign Y6=~^A6; //reduction XNOR
endmodule

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tests/hana/test_intermout_exprs_sub_test.v
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module test(out, in1, in2, vin1, vin2, vout1);
output out;
input in1, in2;
input [1:0] vin1;
input [2:0] vin2;
output [3:0] vout1;
assign out = in1 - in2;
assign vout1 = vin1 - vin2;
endmodule

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tests/hana/test_intermout_exprs_unaryminus_test.v
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module test(output out, input in, output [31:0] vout, input [31:0] vin);
assign out = -in;
assign vout = -vin;
endmodule

4
tests/hana/test_intermout_exprs_unaryplus_test.v
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module test(output out, input in);
assign out = +in;
endmodule

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tests/hana/test_intermout_exprs_varshift_test.v
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module test(vin0, vout0);
input [2:0] vin0;
output reg [7:0] vout0;
wire [7:0] myreg0, myreg1, myreg2;
integer i;
assign myreg0 = vout0 << vin0;
assign myreg1 = myreg2 >> i;
endmodule

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// test_parse2synthtrans_behavopt_1_test.v
module f1_test(in, out, clk, reset);
input in, reset;
output reg out;
input clk;
reg signed [3:0] a;
reg signed [3:0] b;
reg signed [3:0] c;
reg [5:0] d;
reg [5:0] e;
always @(clk or reset) begin
a = -4;
b = 2;
c = a + b;
d = a + b + c;
d = d*d;
if(b)
e = d*d;
else
e = d + d;
end
endmodule
// test_parse2synthtrans_case_1_test.v
module f2_demultiplexer1_to_4 (out0, out1, out2, out3, in, s1, s0);
output out0, out1, out2, out3;
reg out0, out1, out2, out3;
input in;
input s1, s0;
reg [3:0] encoding;
reg [1:0] state;
always @(encoding) begin
case (encoding)
4'bxx11: state = 1;
4'bx0xx: state = 3;
4'b11xx: state = 4;
4'bx1xx: state = 2;
4'bxx1x: state = 1;
4'bxxx1: state = 0;
default: state = 0;
endcase
end
always @(encoding) begin
case (encoding)
4'b0000: state = 1;
default: state = 0;
endcase
end
endmodule
// test_parse2synthtrans_contassign_1_test.v
module f3_test(in, out);
input wire in;
output out;
assign out = (in+in);
assign out = 74;
endmodule
// test_parse2synthtrans_module_basic0_test.v
module f4_test;
endmodule
// test_parse2synthtrans_operators_1_test.v
module f5_test(in, out);
input in;
output out;
parameter p1 = 10;
parameter p2 = 5;
assign out = +p1;
assign out = -p2;
assign out = p1 + p2;
assign out = p1 - p2;
endmodule
// test_parse2synthtrans_param_1_test.v
module f6_test(in, out);
input in;
output out;
parameter p = 10;
assign out = p;
endmodule
// test_parse2synthtrans_port_scalar_1_test.v
module f7_test(in, out, io);
inout io;
output out;
input in;
endmodule
// test_parse2synthtrans_port_vector_1_test.v
module f8_test(in1, in2, out1, out2, io1, io2);
inout [1:0] io1;
inout [0:1] io2;
output [1:0] out1;
output [0:1] out2;
input [1:0] in1;
input [0:1] in2;
endmodule
// test_parse2synthtrans_v2k_comb_logic_sens_list_test.v
module f9_test(q, d, clk, reset);
output reg q;
input d, clk, reset;
always @ (posedge clk, negedge reset)
if(!reset) q <= 0;
else q <= d;
endmodule

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tests/hana/test_parse2synthtrans_behavopt_1_test.v
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module test(in, out, clk, reset);
input in, reset;
output reg out;
input clk;
reg signed [3:0] a;
reg signed [3:0] b;
reg signed [3:0] c;
reg [5:0] d;
reg [5:0] e;
always @(clk or reset) begin
a = -4;
b = 2;
c = a + b;
d = a + b + c;
d = d*d;
if(b)
e = d*d;
else
e = d + d;
end
endmodule

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tests/hana/test_parse2synthtrans_case_1_test.v
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module demultiplexer1_to_4 (out0, out1, out2, out3, in, s1, s0);
output out0, out1, out2, out3;
reg out0, out1, out2, out3;
input in;
input s1, s0;
reg [3:0] encoding;
reg [1:0] state;
always @(encoding) begin
case (encoding)
4'bxx11: state = 1;
4'bx0xx: state = 3;
4'b11xx: state = 4;
4'bx1xx: state = 2;
4'bxx1x: state = 1;
4'bxxx1: state = 0;
default: state = 0;
endcase
end
always @(encoding) begin
case (encoding)
4'b0000: state = 1;
default: state = 0;
endcase
end
endmodule

7
tests/hana/test_parse2synthtrans_contassign_1_test.v
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module test(in, out);
input wire in;
output out;
assign out = (in+in);
assign out = 74;
endmodule

2
tests/hana/test_parse2synthtrans_module_basic0_test.v
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module test;
endmodule

11
tests/hana/test_parse2synthtrans_operators_1_test.v
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module test(in, out);
input in;
output out;
parameter p1 = 10;
parameter p2 = 5;
assign out = +p1;
assign out = -p2;
assign out = p1 + p2;
assign out = p1 - p2;
endmodule

7
tests/hana/test_parse2synthtrans_param_1_test.v
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module test(in, out);
input in;
output out;
parameter p = 10;
assign out = p;
endmodule

6
tests/hana/test_parse2synthtrans_port_scalar_1_test.v
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module test(in, out, io);
inout io;
output out;
input in;
endmodule

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tests/hana/test_parse2synthtrans_port_vector_1_test.v
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module test(in1, in2, out1, out2, io1, io2);
inout [1:0] io1;
inout [0:1] io2;
output [1:0] out1;
output [0:1] out2;
input [1:0] in1;
input [0:1] in2;
endmodule

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tests/hana/test_parse2synthtrans_v2k_comb_logic_sens_list_test.v
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module test(q, d, clk, reset);
output reg q;
input d, clk, reset;
always @ (posedge clk, negedge reset)
if(!reset) q <= 0;
else q <= d;
endmodule

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tests/hana/test_parser.v Normal file
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// test_parser_constructs_module_basic1_test.v
module f1_test;
endmodule
// test_parser_constructs_param_basic0_test.v
module f2_test #( parameter v2kparam = 5)
(in, out, io, vin, vout, vio);
input in;
output out;
inout io;
input [3:0] vin;
output [v2kparam:0] vout;
inout [0:3] vio;
parameter myparam = 10;
endmodule
// test_parser_constructs_port_basic0_test.v
module f3_test(in, out, io, vin, vout, vio);
input in;
output out;
inout io;
input [3:0] vin;
output [3:0] vout;
inout [0:3] vio;
endmodule
// test_parser_directives_define_simpledef_test.v
`define parvez ahmad
`define WIRE wire
`define TEN 10
module f4_`parvez();
parameter param = `TEN;
`WIRE w;
assign w = `TEN;
endmodule
// test_parser_misc_operators_test.v
module f5_test(out, i0, i1, i2, i3, s1, s0);
output out;
input i0, i1, i2, i3;
input s1, s0;
assign out = (~s1 & s0 & i0) |
(~s1 & s0 & i1) |
(s1 & ~s0 & i2) |
(s1 & s0 & i3);
endmodule
module f5_ternaryop(out, i0, i1, i2, i3, s1, s0);
output out;
input i0, i1, i2, i3;
input s1, s0;
assign out = s1 ? (s0 ? i3 : i2) : (s0 ? i1 : i0);
endmodule
module f5_fulladd4(sum, c_out, a, b, c_in);
output [3:0] sum;
output c_out;
input [3:0] a, b;
input c_in;
assign {c_out, sum} = a + b + c_in;
endmodule
// test_parser_v2k_comb_port_data_type_test.v
module f6_adder(sum , co, a, b, ci);
output reg [31:0] sum;
output reg co;
input wire [31:0] a, b;
input wire ci;
endmodule
// test_parser_v2k_comma_sep_sens_list_test.v
module f7_test(q, d, clk, reset);
output reg q;
input d, clk, reset;
always @ (posedge clk, negedge reset)
if(!reset) q <= 0;
else q <= d;
endmodule

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tests/hana/test_parser_constructs_module_basic1_test.v
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module test;
endmodule

10
tests/hana/test_parser_constructs_param_basic0_test.v
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@ -1,10 +0,0 @@
module test #( parameter v2kparam = 5)
(in, out, io, vin, vout, vio);
input in;
output out;
inout io;
input [3:0] vin;
output [v2kparam:0] vout;
inout [0:3] vio;
parameter myparam = 10;
endmodule

8
tests/hana/test_parser_constructs_port_basic0_test.v
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@ -1,8 +0,0 @@
module test(in, out, io, vin, vout, vio);
input in;
output out;
inout io;
input [3:0] vin;
output [3:0] vout;
inout [0:3] vio;
endmodule

9
tests/hana/test_parser_directives_define_simpledef_test.v
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@ -1,9 +0,0 @@
`define parvez ahmad
`define WIRE wire
`define TEN 10
module `parvez();
parameter param = `TEN;
`WIRE w;
assign w = `TEN;
endmodule

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tests/hana/test_parser_misc_operators_test.v
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module test(out, i0, i1, i2, i3, s1, s0);
output out;
input i0, i1, i2, i3;
input s1, s0;
assign out = (~s1 & s0 & i0) |
(~s1 & s0 & i1) |
(s1 & ~s0 & i2) |
(s1 & s0 & i3);
endmodule
module ternaryop(out, i0, i1, i2, i3, s1, s0);
output out;
input i0, i1, i2, i3;
input s1, s0;
assign out = s1 ? (s0 ? i3 : i2) : (s0 ? i1 : i0);
endmodule
module fulladd4(sum, c_out, a, b, c_in);
output [3:0] sum;
output c_out;
input [3:0] a, b;
input c_in;
assign {c_out, sum} = a + b + c_in;
endmodule

6
tests/hana/test_parser_v2k_comb_port_data_type_test.v
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module adder(sum , co, a, b, ci);
output reg [31:0] sum;
output reg co;
input wire [31:0] a, b;
input wire ci;
endmodule

9
tests/hana/test_parser_v2k_comma_sep_sens_list_test.v
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@ -1,9 +0,0 @@
module test(q, d, clk, reset);
output reg q;
input d, clk, reset;
always @ (posedge clk, negedge reset)
if(!reset) q <= 0;
else q <= d;
endmodule

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tests/hana/test_simulation_always.v Normal file
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// test_simulation_always_15_test.v
module f1_test(input [1:0] in, output reg [1:0] out);
always @(in)
out = in;
endmodule
// test_simulation_always_17_test.v
module f2_test(a, b, c, d, z);
input a, b, c, d;
output z;
reg z, temp1, temp2;
always @(a or b or c or d)
begin
temp1 = a ^ b;
temp2 = c ^ d;
z = temp1 ^ temp2;
end
endmodule
// test_simulation_always_18_test.v
module f3_test (in1, in2, out);
input in1, in2;
output reg out;
always @ ( in1 or in2)
if(in1 > in2)
out = in1;
else
out = in2;
endmodule
// test_simulation_always_19_test.v
module f4_test(ctrl, in1, in2, out);
input ctrl;
input in1, in2;
output reg out;
always @ (ctrl or in1 or in2)
if(ctrl)
out = in1 & in2;
else
out = in1 | in2;
endmodule
// test_simulation_always_1_test.v
module f5_test(input in, output reg out);
always @(in)
out = in;
endmodule
// test_simulation_always_20_test.v
module f6_NonBlockingEx(clk, merge, er, xmit, fddi, claim);
input clk, merge, er, xmit, fddi;
output reg claim;
reg fcr;
always @(posedge clk)
begin
fcr <= er | xmit;
if(merge)
claim <= fcr & fddi;
else
claim <= fddi;
end
endmodule
// test_simulation_always_21_test.v
module f7_FlipFlop(clk, cs, ns);
input clk;
input [7:0] cs;
output [7:0] ns;
integer is;
always @(posedge clk)
is <= cs;
assign ns = is;
endmodule
// test_simulation_always_22_test.v
module f8_inc(clock, counter);
input clock;
output reg [7:0] counter;
always @(posedge clock)
counter <= counter + 1;
endmodule
// test_simulation_always_23_test.v
module f9_MyCounter (clock, preset, updown, presetdata, counter);
input clock, preset, updown;
input [1: 0] presetdata;
output reg [1:0] counter;
always @(posedge clock)
if(preset)
counter <= presetdata;
else
if(updown)
counter <= counter + 1;
else
counter <= counter - 1;
endmodule
// test_simulation_always_27_test.v
module f10_FlipFlop(clock, cs, ns);
input clock;
input cs;
output reg ns;
reg temp;
always @(posedge clock)
begin
temp <= cs;
ns <= temp;
end
endmodule
// test_simulation_always_29_test.v
module f11_test(input in, output reg [1:0] out);
always @(in)
begin
out = in;
out = out + in;
end
endmodule

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tests/hana/test_simulation_always_15_test.v
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module test(input [1:0] in, output reg [1:0] out);
always @(in)
out = in;
endmodule

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tests/hana/test_simulation_always_17_test.v
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module test(a, b, c, d, z);
input a, b, c, d;
output z;
reg z, temp1, temp2;
always @(a or b or c or d)
begin
temp1 = a ^ b;
temp2 = c ^ d;
z = temp1 ^ temp2;
end
endmodule

10
tests/hana/test_simulation_always_18_test.v
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@ -1,10 +0,0 @@
module test (in1, in2, out);
input in1, in2;
output reg out;
always @ ( in1 or in2)
if(in1 > in2)
out = in1;
else
out = in2;
endmodule

11
tests/hana/test_simulation_always_19_test.v
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@ -1,11 +0,0 @@
module test(ctrl, in1, in2, out);
input ctrl;
input in1, in2;
output reg out;
always @ (ctrl or in1 or in2)
if(ctrl)
out = in1 & in2;
else
out = in1 | in2;
endmodule

5
tests/hana/test_simulation_always_1_test.v
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@ -1,5 +0,0 @@
module test(input in, output reg out);
always @(in)
out = in;
endmodule

15
tests/hana/test_simulation_always_20_test.v
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module NonBlockingEx(clk, merge, er, xmit, fddi, claim);
input clk, merge, er, xmit, fddi;
output reg claim;
reg fcr;
always @(posedge clk)
begin
fcr <= er | xmit;
if(merge)
claim <= fcr & fddi;
else
claim <= fddi;
end
endmodule

11
tests/hana/test_simulation_always_21_test.v
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module FlipFlop(clk, cs, ns);
input clk;
input [7:0] cs;
output [7:0] ns;
integer is;
always @(posedge clk)
is <= cs;
assign ns = is;
endmodule

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tests/hana/test_simulation_always_22_test.v
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module inc(clock, counter);
input clock;
output reg [7:0] counter;
always @(posedge clock)
counter <= counter + 1;
endmodule

14
tests/hana/test_simulation_always_23_test.v
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module MyCounter (clock, preset, updown, presetdata, counter);
input clock, preset, updown;
input [1: 0] presetdata;
output reg [1:0] counter;
always @(posedge clock)
if(preset)
counter <= presetdata;
else
if(updown)
counter <= counter + 1;
else
counter <= counter - 1;
endmodule

13
tests/hana/test_simulation_always_27_test.v
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@ -1,13 +0,0 @@
module FlipFlop(clock, cs, ns);
input clock;
input cs;
output reg ns;
reg temp;
always @(posedge clock)
begin
temp <= cs;
ns <= temp;
end
endmodule

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tests/hana/test_simulation_always_29_test.v
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module test(input in, output reg [1:0] out);
always @(in)
begin
out = in;
out = out + in;
end
endmodule

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tests/hana/test_simulation_and.v Normal file
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// test_simulation_and_1_test.v
module f1_test(input [1:0] in, output out);
assign out = in[0] & in[1];
endmodule
// test_simulation_and_2_test.v
module f2_test(input [1:0] in, output out);
assign out = in[0] && in[1];
endmodule
// test_simulation_and_3_test.v
module f3_test(input [2:0] in, output out);
assign out = in[0] & in[1] & in[2];
endmodule
// test_simulation_and_4_test.v
module f4_test(input [2:0] in, output out);
assign out = in[0] && in[1] && in[2];
endmodule
// test_simulation_and_5_test.v
module f5_test(input [3:0] in, output out);
assign out = in[0] & in[1] & in[2] & in[3];
endmodule
// test_simulation_and_6_test.v
module f6_test(input [3:0] in, output out);
assign out = in[0] && in[1] && in[2] && in[3];
endmodule
// test_simulation_and_7_test.v
module f7_test(input [3:0] in, output out);
and myand(out, in[0], in[1], in[2], in[3]);
endmodule

3
tests/hana/test_simulation_and_1_test.v
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@ -1,3 +0,0 @@
module test(input [1:0] in, output out);
assign out = in[0] & in[1];
endmodule

3
tests/hana/test_simulation_and_2_test.v
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@ -1,3 +0,0 @@
module test(input [1:0] in, output out);
assign out = in[0] && in[1];
endmodule

3
tests/hana/test_simulation_and_3_test.v
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@ -1,3 +0,0 @@
module test(input [2:0] in, output out);
assign out = in[0] & in[1] & in[2];
endmodule

3
tests/hana/test_simulation_and_4_test.v
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@ -1,3 +0,0 @@
module test(input [2:0] in, output out);
assign out = in[0] && in[1] && in[2];
endmodule

3
tests/hana/test_simulation_and_5_test.v
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@ -1,3 +0,0 @@
module test(input [3:0] in, output out);
assign out = in[0] & in[1] & in[2] & in[3];
endmodule

3
tests/hana/test_simulation_and_6_test.v
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@ -1,3 +0,0 @@
module test(input [3:0] in, output out);
assign out = in[0] && in[1] && in[2] && in[3];
endmodule

3
tests/hana/test_simulation_and_7_test.v
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@ -1,3 +0,0 @@
module test(input [3:0] in, output out);
and myand(out, in[0], in[1], in[2], in[3]);
endmodule

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tests/hana/test_simulation_buffer.v Normal file
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// test_simulation_buffer_1_test.v
module f1_test(input in, output out);
assign out = in;
endmodule
// test_simulation_buffer_2_test.v
module f2_test(input [1:0] in, output [1:0] out);
assign out[0] = in[0];
assign out[1] = in[1];
endmodule
// test_simulation_buffer_3_test.v
module f3_test(input in, output [1:0] out);
assign out[0] = in;
assign out[1] = in;
endmodule

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tests/hana/test_simulation_buffer_1_test.v
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module test(input in, output out);
assign out = in;
endmodule

4
tests/hana/test_simulation_buffer_2_test.v
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module test(input [1:0] in, output [1:0] out);
assign out[0] = in[0];
assign out[1] = in[1];
endmodule

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tests/hana/test_simulation_buffer_3_test.v
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@ -1,4 +0,0 @@
module test(input in, output [1:0] out);
assign out[0] = in;
assign out[1] = in;
endmodule

145
tests/hana/test_simulation_decoder_8_test.v → tests/hana/test_simulation_decoder.v
View file

@ -1,4 +1,147 @@
module test (input [5:0] in, input enable, output reg [63:0] out);
// test_simulation_decoder_2_test.v
module f1_test (input [1:0] in, input enable, output reg out);
always @(in or enable)
if(!enable)
out = 4'b0000;
else begin
case (in)
2'b00 : out = 0 ;
2'b01 : out = 1;
2'b10 : out = 0;
2'b11 : out = 1;
endcase
end
endmodule
// test_simulation_decoder_3_test.v
module f2_test (input [1:0] in, input enable, output reg [2:0] out);
always @(in or enable)
if(!enable)
out = 3'b000;
else begin
case (in)
2'b00 : out = 3'b001 ;
2'b01 : out = 3'b010;
2'b10 : out = 3'b010;
2'b11 : out = 3'b100;
endcase
end
endmodule
// test_simulation_decoder_4_test.v
module f3_test (input [2:0] in, output reg [7:0] out);
always @(in )
case (in)
3'b000 : out = 8'b00000001;
3'b001 : out = 8'b00000010;
3'b010 : out = 8'b00000100;
3'b011 : out = 8'b00001000;
3'b100 : out = 8'b00010000;
3'b101 : out = 8'b00100000;
3'b110 : out = 8'b01000000;
3'b111 : out = 8'b10000000;
endcase
endmodule
// test_simulation_decoder_5_test.v
module f4_test (input [2:0] in, input enable, output reg [7:0] out);
always @(in or enable )
if(!enable)
out = 8'b00000000;
else
case (in)
3'b000 : out = 8'b00000001;
3'b001 : out = 8'b00000010;
3'b010 : out = 8'b00000100;
3'b011 : out = 8'b00001000;
3'b100 : out = 8'b00010000;
3'b101 : out = 8'b00100000;
3'b110 : out = 8'b01000000;
3'b111 : out = 8'b10000000;
endcase
endmodule
// test_simulation_decoder_6_test.v
module f5_test (input [3:0] in, input enable, output reg [15:0] out);
always @(in or enable)
if(!enable)
out = 16'b0000000000000000;
else begin
case (in)
4'b0000 : out = 16'b0000000000000001;
4'b0001 : out = 16'b0000000000000010;
4'b0010 : out = 16'b0000000000000100;
4'b0011 : out = 16'b0000000000001000;
4'b0100 : out = 16'b0000000000010000;
4'b0101 : out = 16'b0000000000100000;
4'b0110 : out = 16'b0000000001000000;
4'b0111 : out = 16'b0000000010000000;
4'b1000 : out = 16'b0000000100000000;
4'b1001 : out = 16'b0000001000000000;
4'b1010 : out = 16'b0000010000000000;
4'b1011 : out = 16'b0000100000000000;
4'b1100 : out = 16'b0001000000000000;
4'b1101 : out = 16'b0010000000000000;
4'b1110 : out = 16'b0100000000000000;
4'b1111 : out = 16'b1000000000000000;
endcase
end
endmodule
// test_simulation_decoder_7_test.v
module f6_test (input [4:0] in, input enable, output reg [31:0] out);
always @(in or enable)
if(!enable)
out = 32'b00000000000000000000000000000000;
else begin
case (in)
5'b00000 : out = 32'b00000000000000000000000000000001;
5'b00001 : out = 32'b00000000000000000000000000000010;
5'b00010 : out = 32'b00000000000000000000000000000100;
5'b00011 : out = 32'b00000000000000000000000000001000;
5'b00100 : out = 32'b00000000000000000000000000010000;
5'b00101 : out = 32'b00000000000000000000000000100000;
5'b00110 : out = 32'b00000000000000000000000001000000;
5'b00111 : out = 32'b00000000000000000000000010000000;
5'b01000 : out = 32'b00000000000000000000000100000000;
5'b01001 : out = 32'b00000000000000000000001000000000;
5'b01010 : out = 32'b00000000000000000000010000000000;
5'b01011 : out = 32'b00000000000000000000100000000000;
5'b01100 : out = 32'b00000000000000000001000000000000;
5'b01101 : out = 32'b00000000000000000010000000000000;
5'b01110 : out = 32'b00000000000000000100000000000000;
5'b01111 : out = 32'b00000000000000001000000000000000;
5'b10000 : out = 32'b00000000000000010000000000000000;
5'b10001 : out = 32'b00000000000000100000000000000000;
5'b10010 : out = 32'b00000000000001000000000000000000;
5'b10011 : out = 32'b00000000000010000000000000000000;
5'b10100 : out = 32'b00000000000100000000000000000000;
5'b10101 : out = 32'b00000000001000000000000000000000;
5'b10110 : out = 32'b00000000010000000000000000000000;
5'b10111 : out = 32'b00000000100000000000000000000000;
5'b11000 : out = 32'b00000001000000000000000000000000;
5'b11001 : out = 32'b00000010000000000000000000000000;
5'b11010 : out = 32'b00000100000000000000000000000000;
5'b11011 : out = 32'b00001000000000000000000000000000;
5'b11100 : out = 32'b00010000000000000000000000000000;
5'b11101 : out = 32'b00100000000000000000000000000000;
5'b11110 : out = 32'b01000000000000000000000000000000;
5'b11111 : out = 32'b10000000000000000000000000000000;
endcase
end
endmodule
// test_simulation_decoder_8_test.v
module f7_test (input [5:0] in, input enable, output reg [63:0] out);
always @(in or enable)
if(!enable)

14
tests/hana/test_simulation_decoder_2_test.v
View file

@ -1,14 +0,0 @@
module test (input [1:0] in, input enable, output reg out);
always @(in or enable)
if(!enable)
out = 4'b0000;
else begin
case (in)
2'b00 : out = 0 ;
2'b01 : out = 1;
2'b10 : out = 0;
2'b11 : out = 1;
endcase
end
endmodule

14
tests/hana/test_simulation_decoder_3_test.v
View file

@ -1,14 +0,0 @@
module test (input [1:0] in, input enable, output reg [2:0] out);
always @(in or enable)
if(!enable)
out = 3'b000;
else begin
case (in)
2'b00 : out = 3'b001 ;
2'b01 : out = 3'b010;
2'b10 : out = 3'b010;
2'b11 : out = 3'b100;
endcase
end
endmodule

14
tests/hana/test_simulation_decoder_4_test.v
View file

@ -1,14 +0,0 @@
module test (input [2:0] in, output reg [7:0] out);
always @(in )
case (in)
3'b000 : out = 8'b00000001;
3'b001 : out = 8'b00000010;
3'b010 : out = 8'b00000100;
3'b011 : out = 8'b00001000;
3'b100 : out = 8'b00010000;
3'b101 : out = 8'b00100000;
3'b110 : out = 8'b01000000;
3'b111 : out = 8'b10000000;
endcase
endmodule

17
tests/hana/test_simulation_decoder_5_test.v
View file

@ -1,17 +0,0 @@
module test (input [2:0] in, input enable, output reg [7:0] out);
always @(in or enable )
if(!enable)
out = 8'b00000000;
else
case (in)
3'b000 : out = 8'b00000001;
3'b001 : out = 8'b00000010;
3'b010 : out = 8'b00000100;
3'b011 : out = 8'b00001000;
3'b100 : out = 8'b00010000;
3'b101 : out = 8'b00100000;
3'b110 : out = 8'b01000000;
3'b111 : out = 8'b10000000;
endcase
endmodule

27
tests/hana/test_simulation_decoder_6_test.v
View file

@ -1,27 +0,0 @@
module test (input [3:0] in, input enable, output reg [15:0] out);
always @(in or enable)
if(!enable)
out = 16'b0000000000000000;
else begin
case (in)
4'b0000 : out = 16'b0000000000000001;
4'b0001 : out = 16'b0000000000000010;
4'b0010 : out = 16'b0000000000000100;
4'b0011 : out = 16'b0000000000001000;
4'b0100 : out = 16'b0000000000010000;
4'b0101 : out = 16'b0000000000100000;
4'b0110 : out = 16'b0000000001000000;
4'b0111 : out = 16'b0000000010000000;
4'b1000 : out = 16'b0000000100000000;
4'b1001 : out = 16'b0000001000000000;
4'b1010 : out = 16'b0000010000000000;
4'b1011 : out = 16'b0000100000000000;
4'b1100 : out = 16'b0001000000000000;
4'b1101 : out = 16'b0010000000000000;
4'b1110 : out = 16'b0100000000000000;
4'b1111 : out = 16'b1000000000000000;
endcase
end
endmodule

43
tests/hana/test_simulation_decoder_7_test.v
View file

@ -1,43 +0,0 @@
module test (input [4:0] in, input enable, output reg [31:0] out);
always @(in or enable)
if(!enable)
out = 32'b00000000000000000000000000000000;
else begin
case (in)
5'b00000 : out = 32'b00000000000000000000000000000001;
5'b00001 : out = 32'b00000000000000000000000000000010;
5'b00010 : out = 32'b00000000000000000000000000000100;
5'b00011 : out = 32'b00000000000000000000000000001000;
5'b00100 : out = 32'b00000000000000000000000000010000;
5'b00101 : out = 32'b00000000000000000000000000100000;
5'b00110 : out = 32'b00000000000000000000000001000000;
5'b00111 : out = 32'b00000000000000000000000010000000;
5'b01000 : out = 32'b00000000000000000000000100000000;
5'b01001 : out = 32'b00000000000000000000001000000000;
5'b01010 : out = 32'b00000000000000000000010000000000;
5'b01011 : out = 32'b00000000000000000000100000000000;
5'b01100 : out = 32'b00000000000000000001000000000000;
5'b01101 : out = 32'b00000000000000000010000000000000;
5'b01110 : out = 32'b00000000000000000100000000000000;
5'b01111 : out = 32'b00000000000000001000000000000000;
5'b10000 : out = 32'b00000000000000010000000000000000;
5'b10001 : out = 32'b00000000000000100000000000000000;
5'b10010 : out = 32'b00000000000001000000000000000000;
5'b10011 : out = 32'b00000000000010000000000000000000;
5'b10100 : out = 32'b00000000000100000000000000000000;
5'b10101 : out = 32'b00000000001000000000000000000000;
5'b10110 : out = 32'b00000000010000000000000000000000;
5'b10111 : out = 32'b00000000100000000000000000000000;
5'b11000 : out = 32'b00000001000000000000000000000000;
5'b11001 : out = 32'b00000010000000000000000000000000;
5'b11010 : out = 32'b00000100000000000000000000000000;
5'b11011 : out = 32'b00001000000000000000000000000000;
5'b11100 : out = 32'b00010000000000000000000000000000;
5'b11101 : out = 32'b00100000000000000000000000000000;
5'b11110 : out = 32'b01000000000000000000000000000000;
5'b11111 : out = 32'b10000000000000000000000000000000;
endcase
end
endmodule

42
tests/hana/test_simulation_inc.v Normal file
View file

@ -0,0 +1,42 @@
// test_simulation_inc_16_test.v
module f1_test(input [15:0] in, output [15:0] out);
assign out = -in;
endmodule
// test_simulation_inc_1_test.v
module f2_test(input in, output out);
assign out = -in;
endmodule
// test_simulation_inc_2_test.v
module f3_test(input [1:0] in, output [1:0] out);
assign out = -in;
endmodule
// test_simulation_inc_32_test.v
module f4_test(input [31:0] in, output [31:0] out);
assign out = -in;
endmodule
// test_simulation_inc_4_test.v
module f5_test(input [3:0] in, output [3:0] out);
assign out = -in;
endmodule
// test_simulation_inc_8_test.v
module f6_test(input [7:0] in, output [7:0] out);
assign out = -in;
endmodule

5
tests/hana/test_simulation_inc_16_test.v
View file

@ -1,5 +0,0 @@
module test(input [15:0] in, output [15:0] out);
assign out = -in;
endmodule

5
tests/hana/test_simulation_inc_1_test.v
View file

@ -1,5 +0,0 @@
module test(input in, output out);
assign out = -in;
endmodule

5
tests/hana/test_simulation_inc_2_test.v
View file

@ -1,5 +0,0 @@
module test(input [1:0] in, output [1:0] out);
assign out = -in;
endmodule

5
tests/hana/test_simulation_inc_32_test.v
View file

@ -1,5 +0,0 @@
module test(input [31:0] in, output [31:0] out);
assign out = -in;
endmodule

5
tests/hana/test_simulation_inc_4_test.v
View file

@ -1,5 +0,0 @@
module test(input [3:0] in, output [3:0] out);
assign out = -in;
endmodule

5
tests/hana/test_simulation_inc_8_test.v
View file

@ -1,5 +0,0 @@
module test(input [7:0] in, output [7:0] out);
assign out = -in;
endmodule

13
tests/hana/test_simulation_mod_1_xx.v
View file

@ -1,13 +0,0 @@
module test(in1, in2, out);
input in1;
input in2;
output out;
wire synth_net_0;
wire synth_net_1;
BUF synth_BUF_0(.in(synth_net_1), .out(out
));
DIV1 synth_DIV(.in1(in1), .in2(in2), .rem(synth_net_0), .out(synth_net_1
));
endmodule

176
tests/hana/test_simulation_mux.v Normal file
View file

@ -0,0 +1,176 @@
// test_simulation_mux_16_test.v
module f1_test(input [15:0] in, input [3:0] select, output reg out);
always @( in or select)
case (select)
0: out = in[0];
1: out = in[1];
2: out = in[2];
3: out = in[3];
4: out = in[4];
5: out = in[5];
6: out = in[6];
7: out = in[7];
8: out = in[8];
9: out = in[9];
10: out = in[10];
11: out = in[11];
12: out = in[12];
13: out = in[13];
14: out = in[14];
15: out = in[15];
endcase
endmodule
// test_simulation_mux_2_test.v
module f2_test(input [1:0] in, input select, output reg out);
always @( in or select)
case (select)
0: out = in[0];
1: out = in[1];
endcase
endmodule
// test_simulation_mux_32_test.v
module f3_test(input [31:0] in, input [4:0] select, output reg out);
always @( in or select)
case (select)
0: out = in[0];
1: out = in[1];
2: out = in[2];
3: out = in[3];
4: out = in[4];
5: out = in[5];
6: out = in[6];
7: out = in[7];
8: out = in[8];
9: out = in[9];
10: out = in[10];
11: out = in[11];
12: out = in[12];
13: out = in[13];
14: out = in[14];
15: out = in[15];
16: out = in[16];
17: out = in[17];
18: out = in[18];
19: out = in[19];
20: out = in[20];
21: out = in[21];
22: out = in[22];
23: out = in[23];
24: out = in[24];
25: out = in[25];
26: out = in[26];
27: out = in[27];
28: out = in[28];
29: out = in[29];
30: out = in[30];
31: out = in[31];
endcase
endmodule
// test_simulation_mux_4_test.v
module f4_test(input [3:0] in, input [1:0] select, output reg out);
always @( in or select)
case (select)
0: out = in[0];
1: out = in[1];
2: out = in[2];
3: out = in[3];
endcase
endmodule
// test_simulation_mux_64_test.v
module f5_test(input [63:0] in, input [5:0] select, output reg out);
always @( in or select)
case (select)
0: out = in[0];
1: out = in[1];
2: out = in[2];
3: out = in[3];
4: out = in[4];
5: out = in[5];
6: out = in[6];
7: out = in[7];
8: out = in[8];
9: out = in[9];
10: out = in[10];
11: out = in[11];
12: out = in[12];
13: out = in[13];
14: out = in[14];
15: out = in[15];
16: out = in[16];
17: out = in[17];
18: out = in[18];
19: out = in[19];
20: out = in[20];
21: out = in[21];
22: out = in[22];
23: out = in[23];
24: out = in[24];
25: out = in[25];
26: out = in[26];
27: out = in[27];
28: out = in[28];
29: out = in[29];
30: out = in[30];
31: out = in[31];
32: out = in[32];
33: out = in[33];
34: out = in[34];
35: out = in[35];
36: out = in[36];
37: out = in[37];
38: out = in[38];
39: out = in[39];
40: out = in[40];
41: out = in[41];
42: out = in[42];
43: out = in[43];
44: out = in[44];
45: out = in[45];
46: out = in[46];
47: out = in[47];
48: out = in[48];
49: out = in[49];
50: out = in[50];
51: out = in[51];
52: out = in[52];
53: out = in[53];
54: out = in[54];
55: out = in[55];
56: out = in[56];
57: out = in[57];
58: out = in[58];
59: out = in[59];
60: out = in[60];
61: out = in[61];
62: out = in[62];
63: out = in[63];
endcase
endmodule
// test_simulation_mux_8_test.v
module f6_test(input [7:0] in, input [2:0] select, output reg out);
always @( in or select)
case (select)
0: out = in[0];
1: out = in[1];
2: out = in[2];
3: out = in[3];
4: out = in[4];
5: out = in[5];
6: out = in[6];
7: out = in[7];
endcase
endmodule

22
tests/hana/test_simulation_mux_16_test.v
View file

@ -1,22 +0,0 @@
module test(input [15:0] in, input [3:0] select, output reg out);
always @( in or select)
case (select)
0: out = in[0];
1: out = in[1];
2: out = in[2];
3: out = in[3];
4: out = in[4];
5: out = in[5];
6: out = in[6];
7: out = in[7];
8: out = in[8];
9: out = in[9];
10: out = in[10];
11: out = in[11];
12: out = in[12];
13: out = in[13];
14: out = in[14];
15: out = in[15];
endcase
endmodule

8
tests/hana/test_simulation_mux_2_test.v
View file

@ -1,8 +0,0 @@
module test(input [1:0] in, input select, output reg out);
always @( in or select)
case (select)
0: out = in[0];
1: out = in[1];
endcase
endmodule

39
tests/hana/test_simulation_mux_32_test.v
View file

@ -1,39 +0,0 @@
module test(input [31:0] in, input [4:0] select, output reg out);
always @( in or select)
case (select)
0: out = in[0];
1: out = in[1];
2: out = in[2];
3: out = in[3];
4: out = in[4];
5: out = in[5];
6: out = in[6];
7: out = in[7];
8: out = in[8];
9: out = in[9];
10: out = in[10];
11: out = in[11];
12: out = in[12];
13: out = in[13];
14: out = in[14];
15: out = in[15];
16: out = in[16];
17: out = in[17];
18: out = in[18];
19: out = in[19];
20: out = in[20];
21: out = in[21];
22: out = in[22];
23: out = in[23];
24: out = in[24];
25: out = in[25];
26: out = in[26];
27: out = in[27];
28: out = in[28];
29: out = in[29];
30: out = in[30];
31: out = in[31];
endcase
endmodule

10
tests/hana/test_simulation_mux_4_test.v
View file

@ -1,10 +0,0 @@
module test(input [3:0] in, input [1:0] select, output reg out);
always @( in or select)
case (select)
0: out = in[0];
1: out = in[1];
2: out = in[2];
3: out = in[3];
endcase
endmodule

71
tests/hana/test_simulation_mux_64_test.v
View file

@ -1,71 +0,0 @@
module test(input [63:0] in, input [5:0] select, output reg out);
always @( in or select)
case (select)
0: out = in[0];
1: out = in[1];
2: out = in[2];
3: out = in[3];
4: out = in[4];
5: out = in[5];
6: out = in[6];
7: out = in[7];
8: out = in[8];
9: out = in[9];
10: out = in[10];
11: out = in[11];
12: out = in[12];
13: out = in[13];
14: out = in[14];
15: out = in[15];
16: out = in[16];
17: out = in[17];
18: out = in[18];
19: out = in[19];
20: out = in[20];
21: out = in[21];
22: out = in[22];
23: out = in[23];
24: out = in[24];
25: out = in[25];
26: out = in[26];
27: out = in[27];
28: out = in[28];
29: out = in[29];
30: out = in[30];
31: out = in[31];
32: out = in[32];
33: out = in[33];
34: out = in[34];
35: out = in[35];
36: out = in[36];
37: out = in[37];
38: out = in[38];
39: out = in[39];
40: out = in[40];
41: out = in[41];
42: out = in[42];
43: out = in[43];
44: out = in[44];
45: out = in[45];
46: out = in[46];
47: out = in[47];
48: out = in[48];
49: out = in[49];
50: out = in[50];
51: out = in[51];
52: out = in[52];
53: out = in[53];
54: out = in[54];
55: out = in[55];
56: out = in[56];
57: out = in[57];
58: out = in[58];
59: out = in[59];
60: out = in[60];
61: out = in[61];
62: out = in[62];
63: out = in[63];
endcase
endmodule

14
tests/hana/test_simulation_mux_8_test.v
View file

@ -1,14 +0,0 @@
module test(input [7:0] in, input [2:0] select, output reg out);
always @( in or select)
case (select)
0: out = in[0];
1: out = in[1];
2: out = in[2];
3: out = in[3];
4: out = in[4];
5: out = in[5];
6: out = in[6];
7: out = in[7];
endcase
endmodule

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