mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-07 09:55:20 +00:00
5 lines
64 B
Verilog
5 lines
64 B
Verilog
module test(output out, input in);
|
|
|
|
assign out = +in;
|
|
endmodule
|