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14 lines
182 B
Verilog
14 lines
182 B
Verilog
module test(a, b, c, d, z);
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input a, b, c, d;
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output z;
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reg z, temp1, temp2;
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always @(a or b or c or d)
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begin
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temp1 = a ^ b;
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temp2 = c ^ d;
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z = temp1 ^ temp2;
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end
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endmodule
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