mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-07 09:55:20 +00:00
14 lines
173 B
Verilog
14 lines
173 B
Verilog
module FlipFlop(clock, cs, ns);
|
|
input clock;
|
|
input [3:0] cs;
|
|
output reg [3:0] ns;
|
|
reg [3:0] temp;
|
|
|
|
always @(posedge clock)
|
|
begin
|
|
temp = cs;
|
|
ns = temp;
|
|
end
|
|
|
|
endmodule
|