mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-07 09:55:20 +00:00
11 lines
186 B
Verilog
11 lines
186 B
Verilog
module test(vin0, vout0);
|
|
input [2:0] vin0;
|
|
output reg [7:0] vout0;
|
|
|
|
wire [7:0] myreg0, myreg1, myreg2;
|
|
integer i;
|
|
assign myreg0 = vout0 << vin0;
|
|
|
|
assign myreg1 = myreg2 >> i;
|
|
endmodule
|