mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-07 09:55:20 +00:00
12 lines
179 B
Verilog
12 lines
179 B
Verilog
module NegEdgeClock(q, d, clk, reset);
|
|
input d, clk, reset;
|
|
output reg q;
|
|
|
|
always @(negedge clk or negedge reset)
|
|
if(!reset)
|
|
q <= 1'b0;
|
|
else
|
|
q <= d;
|
|
|
|
endmodule
|