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16 lines
247 B
Verilog
16 lines
247 B
Verilog
module NonBlockingEx(clk, merge, er, xmit, fddi, claim);
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input clk, merge, er, xmit, fddi;
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output reg claim;
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reg fcr;
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always @(posedge clk)
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begin
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fcr <= er | xmit;
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if(merge)
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claim <= fcr & fddi;
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else
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claim <= fddi;
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end
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endmodule
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