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12 lines
151 B
Verilog
12 lines
151 B
Verilog
module FlipFlop(clk, cs, ns);
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input clk;
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input [7:0] cs;
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output [7:0] ns;
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integer is;
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always @(posedge clk)
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is <= cs;
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assign ns = is;
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endmodule
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