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17366 commits 134 branches 69 tags 58 MiB
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2114 commits

Author SHA1 Message Date
Emil J. Tywoniak
2255b3f523 liberty: better twines 2026-06-23 11:38:48 +02:00
Emil J. Tywoniak
e451ceaf5d aigerparse: better twines 2026-06-23 11:38:40 +02:00
Emil J. Tywoniak
71e6e31795 ast, flatten, hierarchy: canonically split hierarchical references into twines 2026-06-23 10:53:35 +02:00
Emil J. Tywoniak
7c73fd62e4 twine: fix replayability, reduce TwineSearch usage 2026-06-22 17:53:19 +02:00
Emil J. Tywoniak
b27432326f WIP migration to twine 2026-06-22 00:27:32 +02:00
Emil J. Tywoniak
84829cb11d rtlil_frontend: fix twine ordering 2026-06-20 18:16:47 +02:00
Emil J. Tywoniak
d974527ab4 rtlil_frontend: allocate meta block 2026-06-19 11:48:44 +02:00
Emil J. Tywoniak
e71ed3007d WIP migration to twine 2026-06-19 11:39:47 +02:00
Emil J. Tywoniak
bffe7a6e57 WIP migration to twine 2026-06-18 21:54:57 +02:00
Emil J. Tywoniak
0c450ce8c8 WIP migration to twine 2026-06-18 19:27:41 +02:00
Emil J. Tywoniak
96b0ba9581 WIP migration to twine 2026-06-17 11:04:03 +02:00
Emil J. Tywoniak
3a5f5c77bf twine: avoid TwinePool::lookup 2026-06-16 22:57:13 +02:00
Emil J. Tywoniak
6f1ca02a90 rtlil_frontend, rtlil_backend: dump statics as strings, comments for src 2026-06-16 12:54:36 +02:00
Emil J. Tywoniak
dcc74755e7 WIP 2026-06-15 11:26:09 +02:00
Emil J. Tywoniak
d22805bd47 WIP 2026-06-12 16:25:07 +02:00
Emil J. Tywoniak
c3ffbf6fae WIP 2026-06-12 00:18:53 +02:00
Emil J. Tywoniak
afdae7b87e WIP 2026-06-11 20:02:02 +02:00
Emil J. Tywoniak
8e522b08c0 WIP 2026-06-11 13:17:54 +02:00
Emil J. Tywoniak
f592f2f3af WIP 2026-06-10 19:22:53 +02:00
Emil J. Tywoniak
2117af318c WIP 2026-06-10 14:54:48 +02:00
Emil J. Tywoniak
d13dfc21f4 WIP 2026-06-10 14:54:48 +02:00
Emil J. Tywoniak
1a8a95b472 rtlil: fix masquerade 2026-06-10 14:54:45 +02:00
Emil J. Tywoniak
e2627b367e rtlil: set Module::design before name at all construction sites 2026-06-10 14:54:39 +02:00
Emil J. Tywoniak
8f8a07efee rtlil: replace AttrObject::meta_idx_ with ObjMeta pointer 2026-06-10 14:54:31 +02:00
Emil J. Tywoniak
ca632e82c4 rtlil: set Module* on inner-process AttrObjects at construction 2026-06-10 14:54:12 +02:00
Emil J. Tywoniak
f1edb571f2 rtlil: evacuate src_id_ from AttrObject to per-Design meta vector 2026-06-10 14:54:05 +02:00
Emil J. Tywoniak
e70eed3296 rtlil: add Module* back-pointer to RTLIL::Memory 2026-06-10 14:53:59 +02:00
Emil J. Tywoniak
3424c00cd0 twine 2026-06-10 14:53:45 +02:00
Emil J. Tywoniak
68bb5c6b94 signorm: disable in passes that use swap_names 2026-05-22 18:37:58 +02:00
Miodrag Milanovic
75dcbe03c6 Convert RTLIL::unescape_id of IdString to unescape() 2026-05-16 19:49:45 +02:00
Miodrag Milanovic
8bbc3c359c Remove id2cstr uses in our code base 2026-05-16 19:49:45 +02:00
Miodrag Milanovic
4a7878b17f Fixing couple more conversion errors 2026-05-14 15:58:58 +02:00
Miodrag Milanovic
9580ebabc5 log_id here was needed for unescaping 2026-05-14 12:35:01 +02:00
Codexplorer
e41b969da2 Refactored uses of log_id() 2026-05-08 20:59:24 -07:00
Christopher D. Leary
390f09b89a Support positional assignment patterns for unpacked arrays 2026-04-23 14:29:38 -07:00
Petter Reinholdtsen
a89e8fd869 Fixed spelling error in message of frontends/ast/genrtlil.cc. 
Patch by Ruben Undheim via the Debian project.  The patch originated
as 0009-Some-spelling-errors-fixed.patch and was dated 2018-07-12
there.

See also issue #5805.
 2026-04-22 04:30:18 +02:00
Lofty
ed5d122174
Merge pull request #5793 from YosysHQ/lofty/abc-refactor-4 
read/write_xaiger2: further cleanup [sc-269]
 2026-04-21 12:13:42 +00:00
Emil J
86448c0001
Merge pull request #5655 from YosysHQ/emil/dffsr-sr-priority-undef 
Undefine set&reset behavior of $dffsr
 2026-04-08 14:22:34 +00:00
Lofty
6d715784cd read_xaiger2: further cleanup 2026-04-08 11:08:59 +01:00
Emil J. Tywoniak
ad7a776d73 genrtlil: even faster removeSignalFromCaseTree 2026-03-18 23:33:35 +01:00
Emil J. Tywoniak
23ce4b8560 genrtlil: faster removeSignalFromCaseTree 2026-03-18 23:33:35 +01:00
Emil J. Tywoniak
85013f9ed3 fixup! read_liberty: model clear_preset_variable correctly 2026-03-06 14:24:18 +01:00
Robert O'Callahan
13d9fffdb9 Work around std::reverse miscompilation with empty range 
This causes problems when compiling with fuzzing instrumenation enabled.
 2026-03-06 02:03:21 +00:00
Emil J
629bf3dffd
Merge pull request #5630 from apullin/array-assignment 
ast: Add support for array-to-array assignment
 2026-03-05 11:10:12 +00:00
Andrew Pullin
6ac8c8cb05 ast: Add support for array-to-array assignment 
This commit adds support for SystemVerilog array-to-array assignment
operations that were previously unsupported:

1. Direct array assignment: `b = a;`
2. Array ternary expressions: `out = sel ? a : b;`

Both single-dimensional and multi-dimensional unpacked arrays are
supported. The implementation expands these array operations during
AST simplification into element-wise assignments.

Example of now-supported syntax:
```systemverilog
wire [7:0] state_regs[8];
wire [7:0] r[8];
wire [7:0] sel[8];
assign sel = condition ? state_regs : r;
```

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
 2026-03-04 21:34:40 -08:00
Emil J
0d7a875675
Merge pull request #5512 from YosysHQ/emil/turbo-celltypes 
celltypes: compile-time lookup tables for internal cells
 2026-03-04 14:47:57 +00:00
Emil J. Tywoniak
ecb8b20f62 yosys: use newcelltypes for yosys_celltypes users 2026-03-04 12:39:44 +01:00
Emil J. Tywoniak
126492742b read_liberty: fix for msvc 2026-03-03 17:34:58 +01:00
Emil J. Tywoniak
22916aaab1 read_liberty: model clear_preset_variable correctly 2026-03-03 10:35:03 +01:00
Emil J. Tywoniak
857bc02710 liberty: warn if dffsr has clear&preset well defined 2026-03-03 10:34:29 +01:00