rtlil: add Module* back-pointer to RTLIL::Memory

frontends/ast/genrtlil.cc

@@ -1567,6 +1567,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				input_error("Memory `%s' with non-constant width or size!\n", str);
 
 			RTLIL::Memory *memory = new RTLIL::Memory;
+			memory->module = current_module;
 			set_src_attr(memory, this);
 			memory->name = str;
 			memory->width = children[0]->range_left - children[0]->range_right + 1;

frontends/json/jsonparse.cc

@@ -604,6 +604,7 @@ void json_import(Design *design, string &modname, JsonNode *node)
 
 			RTLIL::Memory *mem = new RTLIL::Memory;
 			mem->name = memory_name;
+			mem->module = module;
 
 			if (memory_node->type != 'D')
 				log_error("JSON memory node '%s' is not a dictionary.\n", memory_name.unescape());

frontends/rtlil/rtlil_frontend.cc

@@ -680,6 +680,7 @@ struct RTLILFrontendWorker {
 	void parse_memory()
 	{
 		RTLIL::Memory *memory = new RTLIL::Memory;
+		memory->module = current_module;
 		memory->absorb_attrs(&design->src_twines, std::move(attrbuf));
 
 		int width = 1;

frontends/verific/verific.cc

@@ -1625,6 +1625,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 		{
 			RTLIL::Memory *memory = new RTLIL::Memory;
 			memory->name = RTLIL::escape_id(net->Name());
+			memory->module = module;
 			log_assert(module->count_id(memory->name) == 0);
 			module->memories[memory->name] = memory;
 			import_attributes(memory->attributes, net, nl);