mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-26 09:02:37 +00:00
Code Activity

WIP migration to twine

Browse source
This commit is contained in:
Emil J. Tywoniak 2026-06-17 11:04:03 +02:00
parent 25f27026f0
commit 96b0ba9581
51 changed files with 289 additions and 275 deletions
Download patch file Download diff file Expand all files Collapse all files

38
frontends/aiger/aigerparse.cc
View file

@ -269,7 +269,7 @@ end_of_header:
else
log_abort();
RTLIL::Wire* n0 = module->wire(design->twines.lookup(stringf("$aiger%d$0", aiger_autoidx)));
RTLIL::Wire* n0 = module->wire(TwineSearch(&design->twines).find(stringf("$aiger%d$0", aiger_autoidx)));
if (n0)
module->connect(n0, State::S0);
@ -294,7 +294,7 @@ end_of_header:
log_assert(l1 < latches.size());
wire = latches[l1];
} else if (c == 'o') {
wire = module->wire(design->twines.lookup(escaped_s.str()));
wire = module->wire(TwineSearch(&design->twines).find(escaped_s.str()));
log_assert(l1 < outputs.size());
if (wire) {
// Could have been renamed by a latch
@ -347,16 +347,16 @@ RTLIL::Wire* AigerReader::createWireIfNotExists(RTLIL::Module *module, unsigned
const unsigned variable = literal >> 1;
const bool invert = literal & 1;
RTLIL::IdString wire_name(stringf("$aiger%d$%d%s", aiger_autoidx, variable, invert ? "b" : ""));
RTLIL::Wire *wire = module->wire(design->twines.lookup(wire_name.str()));
RTLIL::Wire *wire = module->wire(TwineSearch(&design->twines).find(wire_name.str()));
if (wire) return wire;
log_debug2("Creating %s\n", wire_name.c_str());
wire = module->addWire(Twine{wire_name.str()});
wire->port_input = wire->port_output = false;
if (!invert) return wire;
RTLIL::IdString wire_inv_name(stringf("$aiger%d$%d", aiger_autoidx, variable));
RTLIL::Wire *wire_inv = module->wire(design->twines.lookup(wire_inv_name.str()));
RTLIL::Wire *wire_inv = module->wire(TwineSearch(&design->twines).find(wire_inv_name.str()));
if (wire_inv) {
if (module->cell(design->twines.lookup(wire_inv_name.str()))) return wire;
if (module->cell(TwineSearch(&design->twines).find(wire_inv_name.str()))) return wire;
}
else {
log_debug2("Creating %s\n", wire_inv_name.c_str());
@ -402,7 +402,7 @@ void AigerReader::parse_xaiger()
else
log_abort();
RTLIL::Wire* n0 = module->wire(design->twines.lookup(stringf("$aiger%d$0", aiger_autoidx)));
RTLIL::Wire* n0 = module->wire(TwineSearch(&design->twines).find(stringf("$aiger%d$0", aiger_autoidx)));
if (n0)
module->connect(n0, State::S0);
@ -426,7 +426,7 @@ void AigerReader::parse_xaiger()
uint32_t rootNodeID = parse_xaiger_literal(f);
uint32_t cutLeavesM = parse_xaiger_literal(f);
log_debug2("rootNodeID=%d cutLeavesM=%d\n", rootNodeID, cutLeavesM);
RTLIL::Wire *output_sig = module->wire(design->twines.lookup(stringf("$aiger%d$%d", aiger_autoidx, rootNodeID)));
RTLIL::Wire *output_sig = module->wire(TwineSearch(&design->twines).find(stringf("$aiger%d$%d", aiger_autoidx, rootNodeID)));
log_assert(output_sig);
uint32_t nodeID;
RTLIL::SigSpec input_sig;
@ -437,7 +437,7 @@ void AigerReader::parse_xaiger()
log_debug("\tLUT '$lut$aiger%d$%d' input %d is constant!\n", aiger_autoidx, rootNodeID, cutLeavesM);
continue;
}
RTLIL::Wire *wire = module->wire(design->twines.lookup(stringf("$aiger%d$%d", aiger_autoidx, nodeID)));
RTLIL::Wire *wire = module->wire(TwineSearch(&design->twines).find(stringf("$aiger%d$%d", aiger_autoidx, nodeID)));
log_assert(wire);
input_sig.append(wire);
}
@ -456,7 +456,7 @@ void AigerReader::parse_xaiger()
log_assert(o.wire == nullptr);
lut_mask.set(gray, o.data);
}
RTLIL::Cell *output_cell = module->cell(design->twines.lookup(stringf("$and$aiger%d$%d", aiger_autoidx, rootNodeID)));
RTLIL::Cell *output_cell = module->cell(TwineSearch(&design->twines).find(stringf("$and$aiger%d$%d", aiger_autoidx, rootNodeID)));
log_assert(output_cell);
module->remove(output_cell);
module->addLut(Twine{stringf("$lut$aiger%d$%d", aiger_autoidx, rootNodeID)}, input_sig, output_sig, std::move(lut_mask));
@ -548,7 +548,7 @@ void AigerReader::parse_aiger_ascii()
// Parse latches
RTLIL::Wire *clk_wire = nullptr;
if (L > 0 && !clk_name.empty()) {
clk_wire = module->wire(design->twines.lookup(clk_name.str()));
clk_wire = module->wire(TwineSearch(&design->twines).find(clk_name.str()));
log_assert(!clk_wire);
log_debug2("Creating %s\n", clk_name.c_str());
clk_wire = module->addWire(Twine{clk_name.str()});
@ -675,7 +675,7 @@ void AigerReader::parse_aiger_binary()
// Parse latches
RTLIL::Wire *clk_wire = nullptr;
if (L > 0 && !clk_name.empty()) {
clk_wire = module->wire(design->twines.lookup(clk_name.str()));
clk_wire = module->wire(TwineSearch(&design->twines).find(clk_name.str()));
log_assert(!clk_wire);
log_debug2("Creating %s\n", clk_name.c_str());
clk_wire = module->addWire(Twine{clk_name.str()});
@ -830,7 +830,7 @@ void AigerReader::post_process()
// Cope with the fact that a CI might be identical
// to a PI (necessary due to ABC); in those cases
// simply connect the latter to the former
existing = module->wire(design->twines.lookup(escaped_s.str()));
existing = module->wire(TwineSearch(&design->twines).find(escaped_s.str()));
if (!existing)
module->rename(wire, design->twines.add(Twine{escaped_s.str()}));
else {
@ -841,7 +841,7 @@ void AigerReader::post_process()
}
else {
RTLIL::IdString indexed_name = stringf("%s[%d]", escaped_s, index);
existing = module->wire(design->twines.lookup(indexed_name.str()));
existing = module->wire(TwineSearch(&design->twines).find(indexed_name.str()));
if (!existing)
module->rename(wire, design->twines.add(Twine{indexed_name.str()}));
else {
@ -875,7 +875,7 @@ void AigerReader::post_process()
// Cope with the fact that a CO might be identical
// to a PO (necessary due to ABC); in those cases
// simply connect the latter to the former
existing = module->wire(design->twines.lookup(escaped_s.str()));
existing = module->wire(TwineSearch(&design->twines).find(escaped_s.str()));
if (!existing)
module->rename(wire, design->twines.add(Twine{escaped_s.str()}));
else {
@ -888,7 +888,7 @@ void AigerReader::post_process()
}
else {
RTLIL::IdString indexed_name = stringf("%s[%d]", escaped_s, index);
existing = module->wire(design->twines.lookup(indexed_name.str()));
existing = module->wire(TwineSearch(&design->twines).find(indexed_name.str()));
if (!existing)
module->rename(wire, design->twines.add(Twine{indexed_name.str()}));
else {
@ -912,7 +912,7 @@ void AigerReader::post_process()
}
}
else if (type == "box") {
RTLIL::Cell* cell = module->cell(design->twines.lookup(stringf("$box%d", variable)));
RTLIL::Cell* cell = module->cell(TwineSearch(&design->twines).find(stringf("$box%d", variable)));
if (!cell)
log_debug("Box %d (%s) no longer exists.\n", variable, log_id(escaped_s));
else
@ -930,7 +930,7 @@ void AigerReader::post_process()
if (min == 0 && max == 0)
continue;
RTLIL::Wire *wire = module->wire(design->twines.lookup(name.str()));
RTLIL::Wire *wire = module->wire(TwineSearch(&design->twines).find(name.str()));
if (wire)
module->rename(wire, design->twines.add(Twine{RTLIL::escape_id(stringf("%s[%d]", name.str(), 0))}));
@ -939,7 +939,7 @@ void AigerReader::post_process()
bool port_input = false, port_output = false;
for (int i = min; i <= max; i++) {
RTLIL::IdString other_name = name.str() + stringf("[%d]", i);
RTLIL::Wire *other_wire = module->wire(design->twines.lookup(other_name.str()));
RTLIL::Wire *other_wire = module->wire(TwineSearch(&design->twines).find(other_name.str()));
if (other_wire) {
port_input = port_input || other_wire->port_input;
port_output = port_output || other_wire->port_output;
@ -953,7 +953,7 @@ void AigerReader::post_process()
for (int i = min; i <= max; i++) {
RTLIL::IdString other_name = stringf("%s[%d]", name, i);
RTLIL::Wire *other_wire = module->wire(design->twines.lookup(other_name.str()));
RTLIL::Wire *other_wire = module->wire(TwineSearch(&design->twines).find(other_name.str()));
if (other_wire) {
other_wire->port_input = false;
other_wire->port_output = false;

6
frontends/aiger2/xaiger.cc
View file

@ -414,7 +414,7 @@ struct Xaiger2Frontend : public Frontend {
log_error("Bad map file: primary output literal out of range\n");
if (bits[lit] == RTLIL::Sm)
log_error("Bad map file: primary output literal is a marker\n");
Wire *w = module->wire(design->twines.lookup(name));
Wire *w = module->wire(TwineSearch(&design->twines).find(name));
if (!w || woffset < 0 || woffset >= w->width)
log_error("Map file references non-existent signal bit %s[%d]\n",
name.c_str(), woffset);
@ -434,8 +434,8 @@ struct Xaiger2Frontend : public Frontend {
log_error("Bad map file: pseudo primary output literal out of range\n");
if (bits[lit] == RTLIL::Sm)
log_error("Bad map file: pseudo primary output literal is a marker\n");
Cell *cell = module->cell(design->twines.lookup(box_name));
auto box_port_ref = design->twines.lookup(box_port);
Cell *cell = module->cell(TwineSearch(&design->twines).find(box_name));
auto box_port_ref = TwineSearch(&design->twines).find(box_port);
if (!cell || !cell->hasPort(box_port_ref))
log_error("Map file references non-existent box port %s/%s\n",
box_name.c_str(), box_port.c_str());

4
frontends/json/jsonparse.cc
View file

@ -357,7 +357,7 @@ void json_import(Design *design, string &modname, JsonNode *node)
if (port_bits_node->type != 'A')
log_error("JSON port node '%s' has non-array bits attribute.\n", port_name.unescape());
Wire *port_wire = module->wire(design->twines.lookup(port_name.str()));
Wire *port_wire = module->wire(TwineSearch(&design->twines).find(port_name.str()));
if (port_wire == nullptr)
port_wire = module->addWire(Twine{port_name.str()}, GetSize(port_bits_node->data_array));
@ -455,7 +455,7 @@ void json_import(Design *design, string &modname, JsonNode *node)
if (bits_node->type != 'A')
log_error("JSON netname node '%s' has non-array bits attribute.\n", net_name.unescape());
Wire *wire = module->wire(design->twines.lookup(net_name.str()));
Wire *wire = module->wire(TwineSearch(&design->twines).find(net_name.str()));
if (wire == nullptr)
wire = module->addWire(Twine{net_name.str()}, GetSize(bits_node->data_array));

10
frontends/liberty/liberty.cc
View file

@ -47,7 +47,7 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *&
return *(expr++) == '0' ? RTLIL::State::S0 : RTLIL::State::S1;
std::string id = RTLIL::escape_id(std::string(expr, id_len));
TwineRef wire_ref = module->design->twines.lookup(id);
TwineRef wire_ref = TwineSearch(&module->design->twines).find(id);
RTLIL::Wire *w = module->wire(wire_ref);
if (!w)
log_error("Can't resolve wire name %s in %s.\n", RTLIL::unescape_id(id), module);
@ -202,8 +202,8 @@ static void create_latch_ff_wires(RTLIL::Module *module, const LibertyAst *node)
static std::pair<RTLIL::SigSpec, RTLIL::SigSpec> find_latch_ff_wires(RTLIL::Module *module, const LibertyAst *node)
{
TwineRef iq_ref = module->design->twines.lookup(RTLIL::escape_id(node->args.at(0)));
TwineRef iqn_ref = module->design->twines.lookup(RTLIL::escape_id(node->args.at(1)));
TwineRef iq_ref = TwineSearch(&module->design->twines).find(RTLIL::escape_id(node->args.at(0)));
TwineRef iqn_ref = TwineSearch(&module->design->twines).find(RTLIL::escape_id(node->args.at(1)));
auto* iq_wire = module->wire(iq_ref);
auto* iqn_wire = module->wire(iqn_ref);
log_assert(iq_wire && iqn_wire);
@ -613,7 +613,7 @@ struct LibertyFrontend : public Frontend {
RTLIL::Module *module = new RTLIL::Module;
module->design = design;
std::string cell_name = RTLIL::escape_id(cell->args.at(0));
TwineRef cell_name_ref = design->twines.lookup(cell_name);
TwineRef cell_name_ref = TwineSearch(&design->twines).find(cell_name);
module->meta_->name = design->twines.add(Twine{cell_name});
if (flag_lib)
@ -734,7 +734,7 @@ struct LibertyFrontend : public Frontend {
if (flag_lib && dir->value == "internal")
continue;
TwineRef wire_ref = module->design->twines.lookup(RTLIL::escape_id(node->args.at(0)));
TwineRef wire_ref = TwineSearch(&module->design->twines).find(RTLIL::escape_id(node->args.at(0)));
RTLIL::Wire *wire = module->wire(wire_ref);
log_assert(wire);

2
frontends/rpc/rpc_frontend.cc
View file

@ -179,7 +179,7 @@ struct RpcModule : RTLIL::Module {
else
derived_name = "$paramod" + stripped_name + parameter_info;
if (design->has(design->twines.lookup(derived_name))) {
if (design->has(TwineSearch(&design->twines).find(derived_name))) {
log("Found cached RTLIL representation for module `%s'.\n", derived_name);
} else {
std::string command, input;