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aigerparse: better twines

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This commit is contained in:
Emil J. Tywoniak 2026-06-23 11:38:40 +02:00
parent 71e6e31795
commit e451ceaf5d
1 changed files with 5 additions and 6 deletions
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11
frontends/aiger/aigerparse.cc
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@ -426,12 +426,11 @@ void AigerReader::parse_xaiger()
uint32_t lutSize = parse_xaiger_literal(f);
log_debug("m: dataSize=%u lutNum=%u lutSize=%u\n", dataSize, lutNum, lutSize);
ConstEvalAig ce(module);
TwineSearch search(&design->twines);
for (unsigned i = 0; i < lutNum; ++i) {
uint32_t rootNodeID = parse_xaiger_literal(f);
uint32_t cutLeavesM = parse_xaiger_literal(f);
log_debug2("rootNodeID=%d cutLeavesM=%d\n", rootNodeID, cutLeavesM);
RTLIL::Wire *output_sig = module->wire(search.find(stringf("$aiger%d$%d", aiger_autoidx, rootNodeID)));
RTLIL::Wire *output_sig = module->wire(design->twines.find(stringf("$aiger%d$%d", aiger_autoidx, rootNodeID)));
log_assert(output_sig);
uint32_t nodeID;
RTLIL::SigSpec input_sig;
@ -442,7 +441,7 @@ void AigerReader::parse_xaiger()
log_debug("\tLUT '$lut$aiger%d$%d' input %d is constant!\n", aiger_autoidx, rootNodeID, cutLeavesM);
continue;
}
RTLIL::Wire *wire = module->wire(search.find(stringf("$aiger%d$%d", aiger_autoidx, nodeID)));
RTLIL::Wire *wire = module->wire(design->twines.find(stringf("$aiger%d$%d", aiger_autoidx, nodeID)));
log_assert(wire);
input_sig.append(wire);
}
@ -461,7 +460,7 @@ void AigerReader::parse_xaiger()
log_assert(o.wire == nullptr);
lut_mask.set(gray, o.data);
}
RTLIL::Cell *output_cell = module->cell(search.find(stringf("$and$aiger%d$%d", aiger_autoidx, rootNodeID)));
RTLIL::Cell *output_cell = module->cell(design->twines.find(stringf("$and$aiger%d$%d", aiger_autoidx, rootNodeID)));
log_assert(output_cell);
module->remove(output_cell);
module->addLut(Twine{stringf("$lut$aiger%d$%d", aiger_autoidx, rootNodeID)}, input_sig, output_sig, std::move(lut_mask));
@ -553,7 +552,7 @@ void AigerReader::parse_aiger_ascii()
// Parse latches
RTLIL::Wire *clk_wire = nullptr;
if (L > 0 && !clk_name.empty()) {
clk_wire = module->wire(TwineSearch(&design->twines).find(clk_name.str()));
clk_wire = module->wire(design->twines.find(clk_name.str()));
log_assert(!clk_wire);
log_debug2("Creating %s\n", clk_name.c_str());
clk_wire = module->addWire(design->twines.add(std::string{clk_name.str()}));
@ -680,7 +679,7 @@ void AigerReader::parse_aiger_binary()
// Parse latches
RTLIL::Wire *clk_wire = nullptr;
if (L > 0 && !clk_name.empty()) {
clk_wire = module->wire(TwineSearch(&design->twines).find(clk_name.str()));
clk_wire = module->wire(design->twines.find(clk_name.str()));
log_assert(!clk_wire);
log_debug2("Creating %s\n", clk_name.c_str());
clk_wire = module->addWire(design->twines.add(std::string{clk_name.str()}));