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WIP migration to twine

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This commit is contained in:
Emil J. Tywoniak 2026-06-18 19:27:41 +02:00
parent 96b0ba9581
commit 0c450ce8c8
110 changed files with 1225 additions and 1082 deletions
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2
backends/aiger/xaiger.cc
View file

@ -271,7 +271,7 @@ struct XAigerWriter
#ifndef NDEBUG
if (ys_debug(1)) {
static pool<std::pair<IdString,TimingInfo::NameBit>> seen;
static pool<std::pair<TwineRef,TimingInfo::NameBit>> seen;
if (seen.emplace(inst_name_id, i.first).second) log("%s.%s[%d] abc9_arrival = %d\n",
cell->type.unescape(), design->twines.unescaped_str(i.first.name), offset, d);
}

9
backends/blif/blif.cc
View file

@ -62,12 +62,13 @@ struct BlifDumper
RTLIL::Design *design;
BlifDumperConfig *config;
NewCellTypes ct;
TwineSearch search;
SigMap sigmap;
dict<SigBit, int> init_bits;
BlifDumper(std::ostream &f, RTLIL::Module *module, RTLIL::Design *design, BlifDumperConfig *config) :
f(f), module(module), design(design), config(config), ct(design), sigmap(module)
f(f), module(module), design(design), config(config), ct(design), search(&design->twines), sigmap(module)
{
for (Wire *wire : module->wires())
if (wire->attributes.count(ID::init)) {
@ -140,7 +141,7 @@ struct BlifDumper
{
if (!config->gates_mode)
return "subckt";
TwineRef cell_type_ref = TwineSearch(&design->twines).find(RTLIL::escape_id(cell_type));
TwineRef cell_type_ref = search.find(RTLIL::escape_id(cell_type));
if (design->module(cell_type_ref) == nullptr)
return "gate";
if (design->module(cell_type_ref)->get_blackbox_attribute())
@ -238,8 +239,8 @@ struct BlifDumper
if (config->unbuf_types.count(cell->type)) {
auto portnames = config->unbuf_types.at(cell->type);
TwineRef port_in = TwineSearch(&design->twines).find(portnames.first.str());
TwineRef port_out = TwineSearch(&design->twines).find(portnames.second.str());
TwineRef port_in = search.find(portnames.first.str());
TwineRef port_out = search.find(portnames.second.str());
f << stringf(".names %s %s\n1 1\n",
str(cell->getPort(port_in)).c_str(), str(cell->getPort(port_out)).c_str());
continue;

3
backends/cxxrtl/cxxrtl_backend.cc
View file

@ -1765,6 +1765,7 @@ struct CxxrtlWorker {
if (!events.empty()) {
f << indent << "if (";
bool first = true;
TwineSearch search(&proc->module->design->twines);
for (auto &event : events) {
if (!first)
f << " || ";
@ -1776,7 +1777,7 @@ struct CxxrtlWorker {
for (auto &action : sync->actions)
dump_assign(action, for_debug);
for (auto &memwr : sync->mem_write_actions) {
TwineRef memid_ref = TwineSearch(&proc->module->design->twines).find(memwr.memid.str());
TwineRef memid_ref = search.find(memwr.memid.str());
log_assert(memid_ref != Twine::Null);
RTLIL::Memory *memory = proc->module->memories[memid_ref];
std::string valid_index_temp = fresh_temporary();

18
backends/edif/edif.cc
View file

@ -30,9 +30,9 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
#define EDIF_DEF(_id) design->twines.unescaped_str(edif_names(_id), true)
#define EDIF_DEFR(_id, _ren, _bl, _br) design->twines.unescaped_str(edif_names(_id), true, _ren, _bl, _br)
#define EDIF_REF(_id) design->twines.unescaped_str(edif_names(_id), false)
#define EDIF_DEF(_id) edif_names(_id.unescape(), true)
#define EDIF_DEFR(_id, _ren, _bl, _br) edif_names(_id.unescape(), true, _ren, _bl, _br)
#define EDIF_REF(_id) edif_names(_id.unescape(), false)
#define EDIF_DEF_STR(_id) edif_names(RTLIL::unescape_id(_id), true)
#define EDIF_REF_STR(_id) edif_names(RTLIL::unescape_id(_id), false)
@ -138,7 +138,7 @@ struct EdifBackend : public Backend {
bool port_rename = false;
bool attr_properties = false;
bool lsbidx = false;
std::map<RTLIL::IdString, std::map<TwineRef, int>> lib_cell_ports;
std::map<TwineRef, std::map<TwineRef, int>> lib_cell_ports;
bool nogndvcc = false, gndvccy = false, keepmode = false;
NewCellTypes ct(design);
EdifNames edif_names;
@ -194,7 +194,7 @@ struct EdifBackend : public Backend {
for (auto module : design->modules())
{
IdString module_type = IdString(design->twines.str(module->meta_->name));
TwineRef module_type = module->meta_->name;
lib_cell_ports[module_type];
for (auto port : module->ports)
@ -220,9 +220,9 @@ struct EdifBackend : public Backend {
continue;
if (design->module(cell->type_impl) == nullptr || design->module(cell->type_impl)->get_blackbox_attribute()) {
lib_cell_ports[cell->type];
lib_cell_ports[cell->type_impl];
for (auto p : cell->connections())
lib_cell_ports[cell->type][p.first] = std::max(lib_cell_ports[cell->type][p.first], GetSize(p.second));
lib_cell_ports[cell->type_impl][p.first] = std::max(lib_cell_ports[cell->type_impl][p.first], GetSize(p.second));
}
}
}
@ -261,7 +261,7 @@ struct EdifBackend : public Backend {
}
for (auto &cell_it : lib_cell_ports) {
*f << stringf(" (cell %s\n", EDIF_DEF(cell_it.first));
*f << stringf(" (cell %s\n", edif_names(design->twines.unescaped_str(cell_it.first), true));
*f << stringf(" (cellType GENERIC)\n");
*f << stringf(" (view VIEW_NETLIST\n");
*f << stringf(" (viewType NETLIST)\n");
@ -478,7 +478,7 @@ struct EdifBackend : public Backend {
for (auto cell : module->cells()) {
*f << stringf(" (instance %s\n", EDIF_DEF(cell->name));
*f << stringf(" (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type),
lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : "");
lib_cell_ports.count(cell->type_impl) > 0 ? " (libraryRef LIB)" : "");
for (auto &p : cell->parameters)
add_prop(p.first, p.second);
if (attr_properties)

14
backends/firrtl/firrtl.cc
View file

@ -82,7 +82,7 @@ const char *make_id(IdString id)
if (namecache.count(id) != 0)
return namecache.at(id).c_str();
string new_id = design->twines.unescaped_str(id);
string new_id = RTLIL::unescape_id(id);
for (int i = 0; i < GetSize(new_id); i++)
{
@ -991,10 +991,10 @@ struct FirrtlWorker
Const init_data = mem.get_init_data();
if (!init_data.is_fully_undef())
log_error("Memory with initialization data: %s.%s\n", module, design->twines.unescaped_str(mem.memid));
log_error("Memory with initialization data: %s.%s\n", module, RTLIL::unescape_id(mem.memid));
if (mem.start_offset != 0)
log_error("Memory with nonzero offset: %s.%s\n", module, design->twines.unescaped_str(mem.memid));
log_error("Memory with nonzero offset: %s.%s\n", module, RTLIL::unescape_id(mem.memid));
for (int i = 0; i < GetSize(mem.rd_ports); i++)
{
@ -1002,7 +1002,7 @@ struct FirrtlWorker
string port_name(stringf("%s.r%d", mem_id, i));
if (port.clk_enable)
log_error("Clocked read port %d on memory %s.%s.\n", i, module, design->twines.unescaped_str(mem.memid));
log_error("Clocked read port %d on memory %s.%s.\n", i, module, RTLIL::unescape_id(mem.memid));
std::ostringstream rpe;
@ -1023,12 +1023,12 @@ struct FirrtlWorker
string port_name(stringf("%s.w%d", mem_id, i));
if (!port.clk_enable)
log_error("Unclocked write port %d on memory %s.%s.\n", i, module, design->twines.unescaped_str(mem.memid));
log_error("Unclocked write port %d on memory %s.%s.\n", i, module, RTLIL::unescape_id(mem.memid));
if (!port.clk_polarity)
log_error("Negedge write port %d on memory %s.%s.\n", i, module, design->twines.unescaped_str(mem.memid));
log_error("Negedge write port %d on memory %s.%s.\n", i, module, RTLIL::unescape_id(mem.memid));
for (int i = 1; i < GetSize(port.en); i++)
if (port.en[0] != port.en[i])
log_error("Complex write enable on port %d on memory %s.%s.\n", i, module, design->twines.unescaped_str(mem.memid));
log_error("Complex write enable on port %d on memory %s.%s.\n", i, module, RTLIL::unescape_id(mem.memid));
std::ostringstream wpe;

12
backends/intersynth/intersynth.cc
View file

@ -41,7 +41,7 @@ static std::string netname(std::set<std::string> &conntypes_code, std::set<std::
return stringf("CONST_%d_0x%x", sig.size(), sig.as_int());
}
return design->twines.unescaped_str(sig.as_wire()->name);
return sig.as_wire()->name.unescaped();
}
struct IntersynthBackend : public Backend {
@ -151,8 +151,8 @@ struct IntersynthBackend : public Backend {
if (wire->port_input || wire->port_output) {
celltypes_code.insert(stringf("celltype !%s b%d %sPORT\n" "%s %s %d %s PORT\n",
wire->name.unescape(), wire->width, wire->port_input ? "*" : "",
wire->port_input ? "input" : "output", design->twines.unescaped_str(wire->name), wire->width, design->twines.unescaped_str(wire->name)));
netlists_code += stringf("node %s %s PORT %s\n", design->twines.unescaped_str(wire->name), design->twines.unescaped_str(wire->name),
wire->port_input ? "input" : "output", wire->name.unescaped(), wire->width, wire->name.unescaped()));
netlists_code += stringf("node %s %s PORT %s\n", wire->name.unescaped(), wire->name.unescaped(),
netname(conntypes_code, celltypes_code, constcells_code, sigmap(wire)).c_str());
}
}
@ -177,13 +177,13 @@ struct IntersynthBackend : public Backend {
}
}
for (auto &param : cell->parameters) {
celltype_code += stringf(" cfg:%d %s", int(param.second.size()), design->twines.unescaped_str(param.first));
celltype_code += stringf(" cfg:%d %s", int(param.second.size()), RTLIL::unescape_id(param.first));
if (param.second.size() != 32) {
node_code += stringf(" %s '", design->twines.unescaped_str(param.first));
node_code += stringf(" %s '", RTLIL::unescape_id(param.first));
for (int i = param.second.size()-1; i >= 0; i--)
node_code += param.second[i] == State::S1 ? "1" : "0";
} else
node_code += stringf(" %s 0x%x", design->twines.unescaped_str(param.first), param.second.as_int());
node_code += stringf(" %s 0x%x", RTLIL::unescape_id(param.first), param.second.as_int());
}
celltypes_code.insert(celltype_code + "\n");

6
backends/jny/jny.cc
View file

@ -91,7 +91,7 @@ struct JnyWriter
{
_cells.clear();
for (auto cell : mod->cells()) {
const auto cell_type = design->twines.unescaped_str(escape_string(cell->type));
const auto cell_type = escape_string(cell->type.unescape());
if (_cells.find(cell_type) == _cells.end())
_cells.emplace(cell_type, std::vector<Cell*>());
@ -353,10 +353,10 @@ struct JnyWriter
f << stringf(",\n");
const auto param_val = param.second;
if (!param_val.empty()) {
f << stringf(" %s\"%s\": ", _indent, design->twines.unescaped_str(escape_string(param.first)));
f << stringf(" %s\"%s\": ", _indent, escape_string(RTLIL::unescape_id(param.first)));
write_param_val(param_val);
} else {
f << stringf(" %s\"%s\": true", _indent, design->twines.unescaped_str(escape_string(param.first)));
f << stringf(" %s\"%s\": true", _indent, escape_string(RTLIL::unescape_id(param.first)));
}
first_param = false;

2
backends/json/json.cc
View file

@ -76,7 +76,7 @@ struct JsonWriter
string get_name(IdString name)
{
return design->twines.unescaped_str(get_string(name));
return get_string(RTLIL::unescape_id(name));
}
string get_name(TwineRef name)

2
backends/rtlil/rtlil_backend.cc
View file

@ -202,7 +202,7 @@ void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::
dump_attributes(f, indent, wire, design, stringify);
if (wire->driverCell_) {
f << stringf("%s" "# driver %s %s\n", indent,
wire->driverCell()->name, wire->driverPort());
wire->driverCell()->name, design->twines.str(wire->driverPort()).c_str());
}
f << stringf("%s" "wire ", indent);
if (wire->width != 1)

14
backends/simplec/simplec.cc
View file

@ -312,8 +312,8 @@ struct SimplecWorker
bit2cell[mod][bit].insert(tuple<Cell*, TwineRef, int>(c, conn.first, idx++));
}
if (design->module(c->type))
create_module_struct(design->module(c->type));
if (design->module(c->type_impl))
create_module_struct(design->module(c->type_impl));
}
TopoSort<IdString> topo;
@ -336,8 +336,9 @@ struct SimplecWorker
topo.analyze_loops = false;
topo.sort();
TwineSearch search(&design->twines);
for (int i = 0; i < GetSize(topo.sorted); i++)
topoidx[mod->cell(TwineSearch(&design->twines).find(topo.sorted[i].str()))] = i;
topoidx[mod->cell(search.find(topo.sorted[i].str()))] = i;
string ifdef_name = stringf("yosys_simplec_%s_state_t", cid(RTLIL::IdString(design->twines.str(mod->meta_->name))));
@ -369,7 +370,7 @@ struct SimplecWorker
struct_declarations.push_back(stringf(" %s %s; // %s", sigtype(w->width), cid(w->name), w));
for (Cell *c : mod->cells())
if (design->module(c->type))
if (design->module(c->type_impl))
struct_declarations.push_back(stringf(" struct %s_state_t %s; // %s", cid(c->type), cid(c->name), c));
struct_declarations.push_back(stringf("};"));
@ -524,10 +525,12 @@ struct SimplecWorker
for (SigBit bit : dirtysig)
{
if (bit2output[work->module].count(bit) && work->parent)
{
TwineSearch search(&work->parent->module->design->twines);
for (auto outbit : bit2output[work->module][bit])
{
Module *parent_mod = work->parent->module;
Cell *parent_cell = parent_mod->cell(TwineSearch(&parent_mod->design->twines).find(work->hiername.str()));
Cell *parent_cell = parent_mod->cell(search.find(work->hiername.str()));
TwineRef port_name = outbit.wire->meta_->name;
int port_offset = outbit.offset;
@ -542,6 +545,7 @@ struct SimplecWorker
log(" Propagating %s.%s[%d] -> %s.%s[%d].\n", work->log_prefix, bit.wire, bit.offset,
work->parent->log_prefix.c_str(), parent_bit.wire, parent_bit.offset);
}
}
for (auto &port : bit2cell[work->module][bit])
{

11
backends/smt2/smt2.cc
View file

@ -60,7 +60,7 @@ struct Smt2Worker
const char *get_id(IdString n)
{
if (ids.count(n) == 0) {
std::string str = design->twines.unescaped_str(n);
std::string str = RTLIL::unescape_id(n);
for (int i = 0; i < GetSize(str); i++) {
if (str[i] == '\\')
str[i] = '/';
@ -798,7 +798,7 @@ struct Smt2Worker
if (has_async_wr && has_sync_wr)
log_error("Memory %s.%s has mixed clocked/nonclocked write ports. This is not supported by \"write_smt2\".\n", cell, module);
decls.push_back(stringf("; yosys-smt2-memory %s %d %d %d %d %s\n", design->twines.unescaped_str(mem->memid), abits, mem->width, GetSize(mem->rd_ports), GetSize(mem->wr_ports), has_async_wr ? "async" : "sync"));
decls.push_back(stringf("; yosys-smt2-memory %s %d %d %d %d %s\n", RTLIL::unescape_id(mem->memid), abits, mem->width, GetSize(mem->rd_ports), GetSize(mem->wr_ports), has_async_wr ? "async" : "sync"));
decls.push_back(witness_memory(get_id(mem->memid), cell, mem));
string memstate;
@ -823,7 +823,7 @@ struct Smt2Worker
if (port.clk_enable)
log_error("Read port %d (%s) of memory %s.%s is clocked. This is not supported by \"write_smt2\"! "
"Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(port.data), design->twines.unescaped_str(mem->memid), module);
"Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(port.data), RTLIL::unescape_id(mem->memid), module);
decls.push_back(stringf("(define-fun |%s_m:R%dA %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
get_id(module), i, get_id(mem->memid), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
@ -867,7 +867,7 @@ struct Smt2Worker
if (port.clk_enable)
log_error("Read port %d (%s) of memory %s.%s is clocked. This is not supported by \"write_smt2\"! "
"Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(port.data), design->twines.unescaped_str(mem->memid), module);
"Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(port.data), RTLIL::unescape_id(mem->memid), module);
decls.push_back(stringf("(define-fun |%s_m:R%dA %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
get_id(module), i, get_id(mem->memid), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
@ -1864,10 +1864,11 @@ struct Smt2Backend : public Backend {
// extract module dependencies
std::map<RTLIL::Module*, std::set<RTLIL::Module*>> module_deps;
TwineSearch search(&design->twines);
for (auto mod : design->modules()) {
module_deps[mod] = std::set<RTLIL::Module*>();
for (auto cell : mod->cells()) {
TwineRef cell_type_ref = TwineSearch(&design->twines).find(cell->type.str());
TwineRef cell_type_ref = search.find(cell->type.str());
if (cell_type_ref != Twine::Null && design->has(cell_type_ref))
module_deps[mod].insert(design->module(cell_type_ref));
}

3
backends/smv/smv.cc
View file

@ -776,6 +776,7 @@ struct SmvBackend : public Backend {
if (template_f.is_open())
{
std::string line;
TwineSearch search(&design->twines);
while (std::getline(template_f, line))
{
int indent = 0;
@ -791,7 +792,7 @@ struct SmvBackend : public Backend {
if (GetSize(stmt) == 2 && stmt[0] == "%module")
{
Module *module = design->module(RTLIL::escape_id(stmt[1]));
Module *module = design->module(search.find(stmt[1]));
modules.erase(module);
if (module == nullptr)

5
backends/spice/spice.cc
View file

@ -30,7 +30,7 @@ PRIVATE_NAMESPACE_BEGIN
static string spice_id2str(IdString id)
{
static const char *escape_chars = "$\\[]()<>=";
string s = design->twines.unescaped_str(id);
string s = RTLIL::unescape_id(id);
for (auto &ch : s)
if (strchr(escape_chars, ch) != nullptr) ch = '_';
@ -101,10 +101,11 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De
ports.at(wire->port_id-1) = wire;
}
TwineSearch search(&design->twines);
for (RTLIL::Wire *wire : ports) {
log_assert(wire != NULL);
RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width);
TwineRef wire_name_ref = TwineSearch(&design->twines).find(wire->name.str());
TwineRef wire_name_ref = search.find(wire->name.str());
if (cell->hasPort(wire_name_ref)) {
sig = sigmap(cell->getPort(wire_name_ref));
sig.extend_u0(wire->width, false);

2
backends/table/table.cc
View file

@ -78,7 +78,7 @@ struct TableBackend : public Backend {
continue;
*f << design->twines.str(module->meta_->name) << "\t";
*f << design->twines.unescaped_str(wire->name) << "\t";
*f << wire->name.unescaped() << "\t";
*f << "-" << "\t";
*f << "-" << "\t";

2
frontends/aiger/aigerparse.cc
View file

@ -224,7 +224,7 @@ AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString
module = new RTLIL::Module;
module->design = design;
module->meta_->name = design->twines.add(Twine{module_name.str()});
if (design->module(design->twines.str(module->meta_->name)))
if (design->module(module->meta_->name))
log_error("Duplicate definition of module %s!\n", design->twines.str(module->meta_->name).c_str());
}

4
frontends/aiger2/xaiger.cc
View file

@ -151,7 +151,7 @@ struct Xaiger2Frontend : public Frontend {
log_error("Map file references non-existent box %s\n",
name.c_str());
Module *def = design->module(box->type);
Module *def = design->module(box->type.ref());
if (def && !box->parameters.empty()) {
// TODO: This is potentially costly even if a cached derivation exists
def = design->module(def->derive(design, box->parameters));
@ -222,7 +222,7 @@ struct Xaiger2Frontend : public Frontend {
std::string port_id_str = design->twines.str(port_id);
for (int j = 0; j < port->width; j++) {
if (conn[j].wire && conn[j].wire->port_output) {
std::string cell_name_str = cell->name.isPublic() ? cell->name.c_str() + 1 : cell->name.c_str();
std::string cell_name_str = cell->name.unescaped();
const char *port_id_str_part = RTLIL::IdString(port_id_str).isPublic() ? port_id_str.c_str() + 1 : port_id_str.c_str();
auto new_wire_name = module->uniquify(design->twines.add(Twine{stringf("$box$%s$%s$%d", cell_name_str.c_str(), port_id_str_part, j)}));
conn[j] = module->addWire(new_wire_name);

18
frontends/blif/blifparse.cc
View file

@ -84,7 +84,7 @@ failed:
return std::pair<RTLIL::IdString, int>(RTLIL::IdString(), 0);
}
void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool run_clean, bool sop_mode, bool wideports)
void parse_blif(RTLIL::Design *design, std::istream &f, TwineRef dff_name, bool run_clean, bool sop_mode, bool wideports)
{
RTLIL::Module *module = nullptr;
RTLIL::Const *lutptr = NULL;
@ -116,11 +116,11 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
}
std::string escaped_name = RTLIL::escape_id(wire_name);
TwineRef wire_ref = TwineSearch(&design->twines).find(escaped_name);
TwineRef wire_ref = design->twines.add(std::string{escaped_name});
Wire *wire = module->wire(wire_ref);
if (wire == nullptr)
wire = module->addWire(design->twines.add(std::string{escaped_name}));
wire = module->addWire(wire_ref);
return wire;
};
@ -206,7 +206,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
for (int i = 0; i < width; i++) {
std::string other_name = design->twines.str(name) + stringf("[%d]", i);
TwineRef other_ref = TwineSearch(&design->twines).find(other_name);
TwineRef other_ref = design->twines.find(other_name);
RTLIL::Wire *other_wire = module->wire(other_ref);
if (other_wire) {
other_wire->port_input = false;
@ -276,10 +276,10 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
while ((p = strtok(NULL, " \t\r\n")) != NULL)
{
std::string wire_name_str = stringf("\\%s", p);
TwineRef wire_ref = TwineSearch(&design->twines).find(wire_name_str);
TwineRef wire_ref = design->twines.add(std::string{wire_name_str});
RTLIL::Wire *wire = module->wire(wire_ref);
if (wire == nullptr)
wire = module->addWire(design->twines.add(std::string{wire_name_str}));
wire = module->addWire(wire_ref);
if (!strcmp(cmd, ".inputs"))
wire->port_input = true;
else
@ -378,10 +378,10 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
cell = module->addDlatchGate(NEW_TWINE, blif_wire(clock), blif_wire(d), blif_wire(q), false);
else {
no_latch_clock:
if (dff_name.empty()) {
if (dff_name == Twine::Null) {
cell = module->addFfGate(NEW_TWINE, blif_wire(d), blif_wire(q));
} else {
cell = module->addCell(NEW_TWINE, design->twines.add(std::string{dff_name.str()}));
cell = module->addCell(NEW_TWINE, dff_name);
cell->setPort(TW::D, blif_wire(d));
cell->setPort(TW::Q, blif_wire(q));
}
@ -698,7 +698,7 @@ struct BlifFrontend : public Frontend {
}
extra_args(f, filename, args, argidx);
parse_blif(design, *f, "", true, sop_mode, wideports);
parse_blif(design, *f, Twine::Null, true, sop_mode, wideports);
}
} BlifFrontend;

2
frontends/blif/blifparse.h
View file

@ -24,7 +24,7 @@
YOSYS_NAMESPACE_BEGIN
extern void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name,
extern void parse_blif(RTLIL::Design *design, std::istream &f, TwineRef dff_name,
bool run_clean = false, bool sop_mode = false, bool wideports = false);
YOSYS_NAMESPACE_END

3
frontends/rpc/rpc_frontend.cc
View file

@ -179,7 +179,8 @@ struct RpcModule : RTLIL::Module {
else
derived_name = "$paramod" + stripped_name + parameter_info;
if (design->has(TwineSearch(&design->twines).find(derived_name))) {
TwineSearch search(&design->twines);
if (design->has(search.find(derived_name))) {
log("Found cached RTLIL representation for module `%s'.\n", derived_name);
} else {
std::string command, input;

11
kernel/constids.inc
View file

@ -306,6 +306,7 @@ X(ACASCREG)
X(ACCUMCI)
X(ACCUMCO)
X(ACIN)
X(ACOUT)
X(AD)
X(ADDEND_NEGATED)
X(ADDR)
@ -334,6 +335,8 @@ X(AOI4)
X(AREG)
X(ARGS)
X(ARGS_WIDTH)
X(ARSHFT17)
X(ARSHFT17_BYPASS)
X(ARST)
X(ARST_POLARITY)
X(ARST_VALUE)
@ -354,6 +357,7 @@ X(B3)
X(B4)
X(BCASCREG)
X(BCIN)
X(BCOUT)
X(BHOLD)
X(BI)
X(BITS_USED)
@ -384,7 +388,9 @@ X(CARRYOUT)
X(CC_L2T4)
X(CC_L2T5)
X(CC_LUT2)
X(CDIN)
X(CDIN_FDBK_SEL)
X(CDOUT)
X(CE)
X(CEA)
X(CEA1)
@ -444,6 +450,8 @@ X(DFF)
X(DHOLD)
X(DIRECTION)
X(DREG)
X(DSP48A)
X(DSP48A1)
X(DSP48E1)
X(DST)
X(DST_EN)
@ -563,6 +571,7 @@ X(LUT5)
X(LUT6)
X(LUT_INIT)
X(M)
X(MACC_PA)
X(MACROCELL_XOR)
X(MASK)
X(MEMID)
@ -610,8 +619,10 @@ X(OUTB_TAP)
X(OVERFLOW)
X(P)
X(PASUB)
X(PASUB_BYPASS)
X(PATTERN)
X(PCIN)
X(PCOUT)
X(PIPELINE_16x16_MULT_REG1)
X(PIPELINE_16x16_MULT_REG2)
X(PORTID)

2
kernel/driver.cc
View file

@ -713,6 +713,8 @@ int main(int argc, char **argv)
total_ns += gc_ns;
timedat.insert(make_tuple(gc_ns,
RTLIL::OwningIdString::garbage_collection_count(), "id_gc"));
total_ns += twine_gc_ns;
timedat.insert(make_tuple(twine_gc_ns, twine_gc_count, "twine_gc"));
total_ns += signorm_ns;
timedat.insert(make_tuple(signorm_ns, signorm_count, "signorm"));
total_ns += signorm_restore_ns;

2
kernel/register.cc
View file

@ -58,6 +58,8 @@ void try_collect_garbage()
return;
garbage_collection_requested = false;
RTLIL::OwningIdString::collect_garbage();
for (auto &[idx, design] : *RTLIL::Design::get_all_designs())
design->gc_twines();
}
Pass::Pass(std::string name, std::string short_help, source_location location) :

136
kernel/rtlil.cc
View file

@ -1225,8 +1225,12 @@ namespace {
}
}
int64_t twine_gc_ns;
int twine_gc_count;
size_t RTLIL::Design::gc_twines()
{
int64_t start = PerformanceTimer::query();
// Mark phase: gather every TwineRef stored on a live object as a root.
// TwinePool::gc traces each root's concat/suffix children transitively.
pool<TwineRef> live;
@ -1264,7 +1268,13 @@ size_t RTLIL::Design::gc_twines()
}
// Sweep: backing refs are stable, so survivors need no remapping.
return twines.gc(live);
size_t erased = twines.gc(live);
int64_t time_ns = PerformanceTimer::query() - start;
Pass::subtract_from_current_runtime_ns(time_ns);
twine_gc_ns += time_ns;
++twine_gc_count;
return erased;
}
pool<std::string> RTLIL::Design::src_leaves(const RTLIL::AttrObject *obj) const
@ -2028,12 +2038,6 @@ namespace {
int param_bool(IdString name)
{
std::cout << name.str() << "\n";
std::cout << "get\n";
for (auto& [key, val] : cell->parameters) {
std::cout << key.str() << " = ";
std::cout << val.as_string() << "\n";
}
int v = param(name);
if (GetSize(cell->parameters.at(name)) > 32)
error(__LINE__);
@ -3772,6 +3776,12 @@ RTLIL::Cell *RTLIL::Module::addCell(TwineRef name, Twine &&type)
return addCell(std::move(name), design->twines.add(std::move(type)));
}
RTLIL::Cell *RTLIL::Module::addCell(Twine name, Twine type)
{
log_assert(design);
return addCell(design->twines.add(std::move(name)), design->twines.add(std::move(type)));
}
RTLIL::Cell *RTLIL::Module::addCell(TwineRef name, const RTLIL::Cell *other)
{
RTLIL::Cell *cell = addCell(name, other->type_impl);
@ -3919,7 +3929,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
cell->setPort(TW::A, sig_a); \
cell->setPort(TW::Y, sig_y); \
cell->set_src_attribute(src); \
static_cast<Derived*>(this)->cell_set_src(cell, src); \
return cell; \
} \
template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed, TwineRef src) { \
@ -3944,7 +3954,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->parameters[ID::WIDTH] = sig_a.size(); \
cell->setPort(TW::A, sig_a); \
cell->setPort(TW::Y, sig_y); \
cell->set_src_attribute(src); \
static_cast<Derived*>(this)->cell_set_src(cell, src); \
return cell; \
} \
template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed, TwineRef src) { \
@ -3966,7 +3976,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::A, sig_a); \
cell->setPort(TW::B, sig_b); \
cell->setPort(TW::Y, sig_y); \
cell->set_src_attribute(src); \
static_cast<Derived*>(this)->cell_set_src(cell, src); \
return cell; \
} \
template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, TwineRef src) { \
@ -4009,7 +4019,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::A, sig_a); \
cell->setPort(TW::B, sig_b); \
cell->setPort(TW::Y, sig_y); \
cell->set_src_attribute(src); \
static_cast<Derived*>(this)->cell_set_src(cell, src); \
return cell; \
} \
template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, TwineRef src) { \
@ -4034,7 +4044,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::A, sig_a); \
cell->setPort(TW::B, sig_b); \
cell->setPort(TW::Y, sig_y); \
cell->set_src_attribute(src); \
static_cast<Derived*>(this)->cell_set_src(cell, src); \
return cell; \
} \
template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, TwineRef src) { \
@ -4054,7 +4064,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::B, sig_b); \
cell->setPort(TW::S, sig_s); \
cell->setPort(TW::Y, sig_y); \
cell->set_src_attribute(src); \
static_cast<Derived*>(this)->cell_set_src(cell, src); \
return cell; \
} \
template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, TwineRef src) { \
@ -4075,7 +4085,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::A, sig_a); \
cell->setPort(TW::S, sig_s); \
cell->setPort(TW::Y, sig_y); \
cell->set_src_attribute(src); \
static_cast<Derived*>(this)->cell_set_src(cell, src); \
return cell; \
} \
template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, TwineRef src) { \
@ -4094,7 +4104,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::A, sig_a); \
cell->setPort(TW::B, sig_b); \
cell->setPort(TW::Y, sig_y); \
cell->set_src_attribute(src); \
static_cast<Derived*>(this)->cell_set_src(cell, src); \
return cell; \
} \
template<typename Derived> RTLIL::SigSpec CellAdderMixin<Derived>::_func(Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, TwineRef src) { \
@ -4110,7 +4120,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), _type); \
cell->setPort(TW::_P1, sig1); \
cell->setPort(TW::_P2, sig2); \
cell->set_src_attribute(src); \
static_cast<Derived*>(this)->cell_set_src(cell, src); \
return cell; \
} \
template<typename Derived> RTLIL::SigBit CellAdderMixin<Derived>::_func(Twine &&name, const RTLIL::SigBit &sig1, TwineRef src) { \
@ -4124,7 +4134,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::_P1, sig1); \
cell->setPort(TW::_P2, sig2); \
cell->setPort(TW::_P3, sig3); \
cell->set_src_attribute(src); \
static_cast<Derived*>(this)->cell_set_src(cell, src); \
return cell; \
} \
template<typename Derived> RTLIL::SigBit CellAdderMixin<Derived>::_func(Twine &&name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, TwineRef src) { \
@ -4139,7 +4149,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::_P2, sig2); \
cell->setPort(TW::_P3, sig3); \
cell->setPort(TW::_P4, sig4); \
cell->set_src_attribute(src); \
static_cast<Derived*>(this)->cell_set_src(cell, src); \
return cell; \
} \
template<typename Derived> RTLIL::SigBit CellAdderMixin<Derived>::_func(Twine &&name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, TwineRef src) { \
@ -4155,7 +4165,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::_P3, sig3); \
cell->setPort(TW::_P4, sig4); \
cell->setPort(TW::_P5, sig5); \
cell->set_src_attribute(src); \
static_cast<Derived*>(this)->cell_set_src(cell, src); \
return cell; \
} \
template<typename Derived> RTLIL::SigBit CellAdderMixin<Derived>::_func(Twine &&name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, TwineRef src) { \
@ -4195,7 +4205,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::A, sig_a);
cell->setPort(TW::B, sig_b);
cell->setPort(TW::Y, sig_y);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4208,7 +4218,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::C, sig_c);
cell->setPort(TW::X, sig_x);
cell->setPort(TW::Y, sig_y);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4220,7 +4230,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->parameters[ID::OFFSET] = offset;
cell->setPort(TW::A, sig_a);
cell->setPort(TW::Y, sig_y);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4232,7 +4242,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::A, sig_a);
cell->setPort(TW::B, sig_b);
cell->setPort(TW::Y, sig_y);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4243,7 +4253,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->parameters[ID::WIDTH] = sig_a.size();
cell->setPort(TW::A, sig_a);
cell->setPort(TW::Y, sig_y);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4254,7 +4264,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::A, sig_a);
cell->setPort(TW::EN, sig_en);
cell->setPort(TW::Y, sig_y);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4263,7 +4273,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), TW($assert));
cell->setPort(TW::A, sig_a);
cell->setPort(TW::EN, sig_en);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4272,7 +4282,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), TW($assume));
cell->setPort(TW::A, sig_a);
cell->setPort(TW::EN, sig_en);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4281,7 +4291,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), TW($live));
cell->setPort(TW::A, sig_a);
cell->setPort(TW::EN, sig_en);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4290,7 +4300,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), TW($fair));
cell->setPort(TW::A, sig_a);
cell->setPort(TW::EN, sig_en);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4299,7 +4309,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), TW($cover));
cell->setPort(TW::A, sig_a);
cell->setPort(TW::EN, sig_en);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4309,7 +4319,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::A, sig_a);
cell->setPort(TW::B, sig_b);
cell->setPort(TW::Y, sig_y);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4322,7 +4332,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::SET, sig_set);
cell->setPort(TW::CLR, sig_clr);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4332,7 +4342,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->parameters[ID::WIDTH] = sig_q.size();
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4344,7 +4354,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::CLK, sig_clk);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4358,7 +4368,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::EN, sig_en);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4375,7 +4385,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::CLR, sig_clr);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4394,7 +4404,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::CLR, sig_clr);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4410,7 +4420,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::ARST, sig_arst);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4428,7 +4438,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::ARST, sig_arst);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4444,7 +4454,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::D, sig_d);
cell->setPort(TW::AD, sig_ad);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4462,7 +4472,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::D, sig_d);
cell->setPort(TW::AD, sig_ad);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4478,7 +4488,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::SRST, sig_srst);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4496,7 +4506,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::SRST, sig_srst);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4514,7 +4524,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::SRST, sig_srst);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4526,7 +4536,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::EN, sig_en);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4542,7 +4552,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::ARST, sig_arst);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4559,7 +4569,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::CLR, sig_clr);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4574,7 +4584,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::S, sig_set);
cell->setPort(TW::R, sig_clr);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4583,7 +4593,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
RTLIL::Cell *cell = static_cast<Derived*>(this)->addCell(std::move(name), TW($_FF_));
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4594,7 +4604,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::C, sig_clk);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4606,7 +4616,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::E, sig_en);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4620,7 +4630,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::R, sig_clr);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4635,7 +4645,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::E, sig_en);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4648,7 +4658,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::R, sig_arst);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4662,7 +4672,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::E, sig_en);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4676,7 +4686,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::D, sig_d);
cell->setPort(TW::AD, sig_ad);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4691,7 +4701,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::D, sig_d);
cell->setPort(TW::AD, sig_ad);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4704,7 +4714,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::R, sig_srst);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4718,7 +4728,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::E, sig_en);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4732,7 +4742,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::E, sig_en);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4743,7 +4753,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::E, sig_en);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4756,7 +4766,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::R, sig_arst);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}
@ -4770,7 +4780,7 @@ RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *o
cell->setPort(TW::R, sig_clr);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
cell->set_src_attribute(src);
static_cast<Derived*>(this)->cell_set_src(cell, src);
return cell;
}

14
kernel/rtlil.h
View file

@ -146,6 +146,8 @@ extern int64_t signorm_ns;
extern int signorm_count;
extern int64_t signorm_restore_ns;
extern int signorm_restore_count;
extern int64_t twine_gc_ns;
extern int twine_gc_count;
struct RTLIL::IdString
{
@ -592,7 +594,10 @@ public:
}
};
inline bool operator==(TwineRef a, RTLIL::IdString b) { return a.untag().value == (size_t)(unsigned)b.index_; }
inline bool operator==(TwineRef a, RTLIL::IdString b) {
size_t bi = (size_t)(unsigned)b.index_;
return bi != 0 && a.untag().value + 1 == bi;
}
inline bool operator==(RTLIL::IdString a, TwineRef b) { return b == a; }
struct RTLIL::OwningIdString : public RTLIL::IdString {
@ -1381,7 +1386,7 @@ struct NameMasqBase {
bool operator==(const Derived &rhs) const { return self().ref() == rhs.ref(); }
bool operator!=(const Derived &rhs) const { return self().ref() != rhs.ref(); }
bool operator<(const Derived &rhs) const { return self().escaped() < rhs.escaped(); }
[[nodiscard]] Hasher hash_into(Hasher h) const { return RTLIL::IdString(self()).hash_into(h); }
[[nodiscard]] Hasher hash_into(Hasher h) const { return self().ref().hash_into(h); }
private:
const Derived &self() const { return *static_cast<const Derived *>(this); }
};
@ -2331,7 +2336,7 @@ public:
friend void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire, const RTLIL::Design *design, bool resolve_src);
RTLIL::Cell *driverCell_ = nullptr;
TwineRef driverPort_;
TwineRef driverPort_ = Twine::Null;
// do not simply copy wires
Wire(ConstructToken, RTLIL::Wire &other);
@ -3160,6 +3165,9 @@ public:
RTLIL::Cell *addCell(TwineRef name, Twine &&type);
RTLIL::Cell *addCell(Twine &&name, const RTLIL::Cell *other);
// CellAdderMixin hook: cells added here are attached, so set src directly.
void cell_set_src(RTLIL::Cell *cell, TwineRef src) { cell->set_src_attribute(src); }
// NEW_ID analog for twine names; see NEW_TWINE in yosys_common.h.
TwineRef new_name(const std::string *prefix) {
TwineRef pref = design->twines.add(Twine{*prefix});

4
kernel/rtlil_bufnorm.cc
View file

@ -1015,6 +1015,10 @@ void RTLIL::Cell::unsetPort(TwineRef portname)
if (bit.is_wire()) {
auto found = fanout.find(bit);
log_assert(found != fanout.end());
// log("debug erasing %s\n", module->design->twines.str(portname));
// log("debug erasing %s %s %d\n", name, module->design->twines.str(portname), i);
// for (auto portbit : found->second)
// log("pb %s %s %d\n", portbit.cell->name, module->design->twines.str(portbit.port), portbit.offset);
int erased = found->second.erase(PortBit(this, portname, i));
log_assert(erased);
if (found->second.empty())

10
kernel/twine.h
View file

@ -108,7 +108,7 @@ struct TW {
}
};
#define TW(id) (size_t)lookup_well_known_id(#id)
#define TW(id) ((size_t)std::integral_constant<int, lookup_well_known_id(#id)>::value)
// #define TW(name) TW::lookup(#name)
struct Twine {
@ -294,6 +294,14 @@ struct TwinePool {
return Twine::Null;
}
// Escaped-name aware: strips a leading '\' and tags the result public,
// mirroring add(std::string), then resolves the content against the
// structural index. Returns Twine::Null if absent.
TwineRef find(const std::string &name) const {
bool is_public = !name.empty() && name[0] == '\\';
return find(Twine{is_public ? name.substr(1) : name}).tag(is_public);
}
TwineRef add_inner(Twine t) {
// Nodes store content only: strip publicity tags off child handles.
if (auto *children = std::get_if<std::vector<TwineRef>>(&t.data)) {

8
kernel/unstable/patch.cc
View file

@ -83,6 +83,8 @@ Wire* Patch::commit_wire(std::unique_ptr<Wire> wire) {
Wire* raw = wire.release();
TwineRef id = twine_staging.resolve(staged_wire_names_.at(raw));
staged_wire_names_.erase(raw);
if (!raw->meta_)
raw->meta_ = mod->design->alloc_obj_meta();
raw->meta_->name = id;
mod->wires_[raw->meta_->name] = raw;
raw->module = mod;
@ -93,9 +95,15 @@ Cell* Patch::commit_cell(std::unique_ptr<Cell> cell) {
Cell* raw = cell.release();
TwineRef id = twine_staging.resolve(staged_cell_names_.at(raw));
staged_cell_names_.erase(raw);
if (!raw->meta_)
raw->meta_ = mod->design->alloc_obj_meta();
raw->meta_->name = id;
raw->module = mod;
mod->cells_[raw->meta_->name] = raw;
if (auto it = staged_cell_src_.find(raw); it != staged_cell_src_.end()) {
raw->set_src_attribute(twine_staging.resolve(it->second));
staged_cell_src_.erase(it);
}
raw->initIndex();
return raw;
}

8
kernel/unstable/patch.h
View file

@ -28,6 +28,7 @@ public:
vector<std::unique_ptr<Cell>> cells_ = {};
TwineChildPool twine_staging;
dict<RTLIL::Cell*, TwineRef> staged_cell_names_;
dict<RTLIL::Cell*, TwineRef> staged_cell_src_;
dict<RTLIL::Wire*, TwineRef> staged_wire_names_;
dict<const std::string*, TwineRef> staged_prefix_cache_;
@ -80,6 +81,13 @@ public:
RTLIL::Cell *addCell(Twine &&name, TwineRef type);
RTLIL::Cell *addCell(TwineRef name, Twine &&type);
// CellAdderMixin hook: staged cells are detached, so record the src and
// apply it once the cell is committed (commit_cell), resolving it through
// twine_staging so the ref may be twine_staging-local (interned without
// touching the per-Design pool). patch()/patch_ports() may still override
// it via apply_src merging from the rewritten cell.
void cell_set_src(RTLIL::Cell *cell, TwineRef src) { if (src != Twine::Null) staged_cell_src_[cell] = src; }
// NEW_ID analog for twine names; see NEW_TWINE in yosys_common.h.
// Returned refs are twine_staging-local and die at the next commit.
TwineRef new_name(const std::string *prefix);

3
passes/cmds/abstract.cc
View file

@ -487,6 +487,7 @@ struct AbstractPass : public Pass {
unsigned int changed = 0;
if ((mode == State) || (mode == Value)) {
TwineSearch search(&design->twines);
for (auto mod : design->selected_modules()) {
EnableLogic enable_logic;
@ -496,7 +497,7 @@ struct AbstractPass : public Pass {
} break;
case Enable::ActiveLow:
case Enable::ActiveHigh: {
Wire *enable_wire = mod->wire(TwineSearch(&mod->design->twines).find("\\" + enable_name));
Wire *enable_wire = mod->wire(search.find("\\" + enable_name));
if (!enable_wire)
log_cmd_error("Enable wire %s not found in module %s\n", enable_name, log_id(mod));
if (GetSize(enable_wire) != 1)

8
passes/cmds/add.cc
View file

@ -35,7 +35,8 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const
std::string escaped_name = RTLIL::escape_id(name);
std::string escaped_enable_name = (enable_name != "") ? RTLIL::escape_id(enable_name) : "";
RTLIL::Design *design = module->design;
RTLIL::Wire *wire = module->wire(TwineSearch(&design->twines).find(escaped_name));
TwineSearch search(&design->twines);
RTLIL::Wire *wire = module->wire(search.find(escaped_name));
log_assert(is_formal_celltype(celltype));
if (wire == nullptr) {
@ -50,7 +51,7 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const
log("Added $%s cell for wire \"%s.%s\"\n", celltype, log_id(module), name);
}
else {
RTLIL::Wire *enable_wire = module->wire(TwineSearch(&design->twines).find(escaped_enable_name));
RTLIL::Wire *enable_wire = module->wire(search.find(escaped_enable_name));
if(enable_wire == nullptr)
log_error("Could not find enable wire with name \"%s\".\n", enable_name);
@ -64,7 +65,8 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
{
RTLIL::Wire *wire = nullptr;
name = RTLIL::escape_id(name);
TwineRef name_ref = TwineSearch(&design->twines).find(name);
TwineSearch search(&design->twines);
TwineRef name_ref = search.find(name);
if (name_ref != Twine::Null)
{

3
passes/cmds/box_derive.cc
View file

@ -77,7 +77,8 @@ struct BoxDerivePass : Pass {
Module *base_override = nullptr;
if (!base_name.empty()) {
base_override = d->module(base_name);
TwineSearch search(&d->twines);
base_override = d->module(search.find(base_name.str()));
if (!base_override)
log_cmd_error("Base module %s not found.\n", base_name.unescape());
}

7
passes/cmds/check.cc
View file

@ -482,10 +482,11 @@ struct CheckPass : public Pass {
// which we have done the edges fallback. The cell and its ports that led to an edge are
// a piece of information we need to recover now. For that we need to have the previous
// wire bit of the loop at hand.
TwineSearch search(&module->design->twines);
SigBit prev;
for (auto it = loop.rbegin(); it != loop.rend(); it++)
if (it->second != -1) { // skip the fallback helper nodes
prev = SigBit(module->wire(TwineSearch(&module->design->twines).find(it->first.str())), it->second);
prev = SigBit(module->wire(search.find(it->first.str())), it->second);
break;
}
log_assert(prev != SigBit());
@ -517,9 +518,9 @@ struct CheckPass : public Pass {
}
};
Wire *wire = module->wire(TwineSearch(&module->design->twines).find(pair.first.str()));
Wire *wire = module->wire(search.find(pair.first.str()));
log_assert(wire);
SigBit bit(module->wire(TwineSearch(&module->design->twines).find(pair.first.str())), pair.second);
SigBit bit(wire, pair.second);
log_assert(driver_cells.count(bit));
Cell *driver = driver_cells.at(bit);

9
passes/cmds/connect.cc
View file

@ -198,17 +198,20 @@ struct ConnectPass : public Pass {
if (flag_nounset)
log_cmd_error("Can't use -port together with -nounset.\n");
if (module->cell(TwineSearch(&module->design->twines).find(RTLIL::escape_id(port_cell))) == nullptr)
TwineSearch search(&module->design->twines);
RTLIL::Cell *port_cell_obj = module->cell(search.find(RTLIL::escape_id(port_cell)));
if (port_cell_obj == nullptr)
log_cmd_error("Can't find cell %s.\n", port_cell);
RTLIL::SigSpec sig;
if (!RTLIL::SigSpec::parse_sel(sig, design, module, port_expr))
log_cmd_error("Failed to parse port expression `%s'.\n", port_expr);
TwineRef port_port_ref = search.find(RTLIL::escape_id(port_port));
if (!flag_assert) {
module->cell(TwineSearch(&module->design->twines).find(RTLIL::escape_id(port_cell)))->setPort(TwineSearch(&module->design->twines).find(RTLIL::escape_id(port_port)), sigmap(sig));
port_cell_obj->setPort(port_port_ref, sigmap(sig));
} else {
SigSpec cur = module->cell(TwineSearch(&module->design->twines).find(RTLIL::escape_id(port_cell)))->getPort(TwineSearch(&module->design->twines).find(RTLIL::escape_id(port_port)));
SigSpec cur = port_cell_obj->getPort(port_port_ref);
if (sigmap(sig) != sigmap(cur)) {
log_cmd_error("Expected connection not present: expected %s, found %s.\n", log_signal(sig), log_signal(cur));
}

10
passes/cmds/copy.cc
View file

@ -44,15 +44,15 @@ struct CopyPass : public Pass {
std::string src_name = RTLIL::escape_id(args[1]);
std::string trg_name = RTLIL::escape_id(args[2]);
if (design->module(src_name) == nullptr)
TwineSearch search(&design->twines);
TwineRef src_ref = search.find(src_name);
if (design->module(src_ref) == nullptr)
log_cmd_error("Can't find source module %s.\n", src_name);
if (design->module(trg_name) != nullptr)
if (design->module(search.find(trg_name)) != nullptr)
log_cmd_error("Target module name %s already exists.\n", trg_name);
RTLIL::Module *new_mod = design->module(src_name)->clone();
design->rename(new_mod, design->twines.add(Twine{trg_name}));
design->add(new_mod);
design->module(src_ref)->clone(design, design->twines.add(std::string{trg_name}));
}
} CopyPass;

3
passes/cmds/delete.cc
View file

@ -100,11 +100,12 @@ struct DeletePass : public Pass {
if (design->selected(module, it.second))
delete_mems.insert(it.first);
TwineSearch search(&design->twines);
for (auto cell : module->cells()) {
if (design->selected(module, cell))
delete_cells.insert(cell);
if (cell->has_memid() &&
delete_mems.count(TwineSearch(&design->twines).find(cell->parameters.at(ID::MEMID).decode_string())) != 0)
delete_mems.count(search.find(cell->parameters.at(ID::MEMID).decode_string())) != 0)
delete_cells.insert(cell);
}

10
passes/cmds/glift.cc
View file

@ -164,7 +164,7 @@ private:
std::vector<RTLIL::SigSpec> next_pmux_y_ports, pmux_y_ports(costs.begin(), costs.begin() + exp2(select_width));
for (auto i = 0; pmux_y_ports.size() > 1; ++i) {
for (auto j = 0; j+1 < GetSize(pmux_y_ports); j += 2) {
next_pmux_y_ports.emplace_back(module->Pmux(Twine{stringf("%s_mux_%d_%d", metamux_select.as_wire()->name.c_str(), i, j)}, pmux_y_ports[j], pmux_y_ports[j+1], metamux_select[GetSize(metamux_select) - 1 - i], metamux_select.as_wire()->src_ref()));
next_pmux_y_ports.emplace_back(module->Pmux(Twine{stringf("%s_mux_%d_%d", metamux_select.as_wire()->name.str().c_str(), i, j)}, pmux_y_ports[j], pmux_y_ports[j+1], metamux_select[GetSize(metamux_select) - 1 - i], metamux_select.as_wire()->src_ref()));
}
if (GetSize(pmux_y_ports) % 2 == 1)
next_pmux_y_ports.push_back(pmux_y_ports[GetSize(pmux_y_ports) - 1]);
@ -207,7 +207,7 @@ private:
int num_versions = opt_instrumentmore? 8 : 4;
for (auto i = 1; i <= num_versions; ++i)
taint_version.emplace_back(RTLIL::SigSpec(module->addWire(Twine{stringf("%s_y%d", cell->name.c_str(), i)}, 1)));
taint_version.emplace_back(RTLIL::SigSpec(module->addWire(Twine{stringf("%s_y%d", cell->name.str().c_str(), i)}, 1)));
for (auto i = 0; i < num_versions; ++i) {
switch(i) {
@ -240,7 +240,7 @@ private:
std::vector<RTLIL::SigSpec> next_meta_mux_y_ports, meta_mux_y_ports(taint_version);
for (auto i = 0; meta_mux_y_ports.size() > 1; ++i) {
for (auto j = 0; j+1 < GetSize(meta_mux_y_ports); j += 2) {
next_meta_mux_y_ports.emplace_back(module->Mux(Twine{stringf("%s_mux_%d_%d", cell->name.c_str(), i, j)}, meta_mux_y_ports[j], meta_mux_y_ports[j+1], meta_mux_select[GetSize(meta_mux_select) - 1 - i]));
next_meta_mux_y_ports.emplace_back(module->Mux(Twine{stringf("%s_mux_%d_%d", cell->name.str().c_str(), i, j)}, meta_mux_y_ports[j], meta_mux_y_ports[j+1], meta_mux_select[GetSize(meta_mux_select) - 1 - i]));
}
if (GetSize(meta_mux_y_ports) % 2 == 1)
next_meta_mux_y_ports.push_back(meta_mux_y_ports[GetSize(meta_mux_y_ports) - 1]);
@ -272,7 +272,7 @@ private:
log_assert(exp2(select_width) == num_versions);
for (auto i = 1; i <= num_versions; ++i)
taint_version.emplace_back(RTLIL::SigSpec(module->addWire(Twine{stringf("%s_y%d", cell->name.c_str(), i)}, 1)));
taint_version.emplace_back(RTLIL::SigSpec(module->addWire(Twine{stringf("%s_y%d", cell->name.str().c_str(), i)}, 1)));
for (auto i = 0; i < num_versions; ++i) {
switch(i) {
@ -295,7 +295,7 @@ private:
std::vector<RTLIL::SigSpec> next_meta_mux_y_ports, meta_mux_y_ports(taint_version);
for (auto i = 0; meta_mux_y_ports.size() > 1; ++i) {
for (auto j = 0; j+1 < GetSize(meta_mux_y_ports); j += 2) {
next_meta_mux_y_ports.emplace_back(module->Mux(Twine{stringf("%s_mux_%d_%d", cell->name.c_str(), i, j)}, meta_mux_y_ports[j], meta_mux_y_ports[j+1], meta_mux_select[GetSize(meta_mux_select) - 1 - i]));
next_meta_mux_y_ports.emplace_back(module->Mux(Twine{stringf("%s_mux_%d_%d", cell->name.str().c_str(), i, j)}, meta_mux_y_ports[j], meta_mux_y_ports[j+1], meta_mux_select[GetSize(meta_mux_select) - 1 - i]));
}
if (GetSize(meta_mux_y_ports) % 2 == 1)
next_meta_mux_y_ports.push_back(meta_mux_y_ports[GetSize(meta_mux_y_ports) - 1]);

2
passes/cmds/icell_liberty.cc
View file

@ -50,7 +50,7 @@ struct LibertyStubber {
auto base_name = base->design->twines.str(base->meta_->name).substr(1);
auto derived_name = derived->design->twines.str(derived->meta_->name).substr(1);
FfTypeData ffType(base_name);
FfTypeData ffType(base->meta_->name);
LibertyItemizer i(f);
if (ffType.has_gclk) {

17
passes/cmds/rename.cc
View file

@ -31,11 +31,12 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std::
from_name = RTLIL::escape_id(from_name);
to_name = RTLIL::escape_id(to_name);
TwineRef to_ref = TwineSearch(&module->design->twines).find(to_name);
TwineSearch search(&module->design->twines);
TwineRef to_ref = search.find(to_name);
if (module->count_id(to_ref))
log_cmd_error("There is already an object `%s' in module `%s'.\n", RTLIL::unescape_id(to_name), log_id(module));
TwineRef from_ref = TwineSearch(&module->design->twines).find(from_name);
TwineRef from_ref = search.find(from_name);
RTLIL::Wire *wire_to_rename = module->wire(from_ref);
RTLIL::Cell *cell_to_rename = module->cell(from_ref);
@ -109,7 +110,8 @@ static IdString derive_name_from_cell_output_wire(const RTLIL::Cell *cell, strin
RTLIL::Wire *wire;
if (move_to_cell) {
TwineRef name_ref = TwineSearch(&cell->module->design->twines).find(name);
TwineSearch search(&cell->module->design->twines);
TwineRef name_ref = search.find(name);
if (name_ref == Twine::Null || (!(wire = cell->module->wire(name_ref)) || !(wire->port_input || wire->port_output)))
return name;
}
@ -140,7 +142,7 @@ static bool rename_witness(RTLIL::Design *design, dict<RTLIL::Module *, int> &ca
bool witness_in_cell = rename_witness(design, cache, impl);
has_witness_signals |= witness_in_cell;
if (witness_in_cell && !cell->name.isPublic()) {
std::string name = cell->name.c_str() + 1;
std::string name = cell->name.unescaped();
for (auto &c : name)
if ((c < 'a' || c > 'z') && (c < 'A' || c > 'Z') && (c < '0' || c > '9') && c != '_')
c = '_';
@ -419,13 +421,14 @@ struct RenamePass : public Pass {
extra_args(args, argidx, design);
for (auto module : design->selected_modules()) {
TwineSearch search(&module->design->twines);
dict<RTLIL::Cell *, IdString> new_cell_names;
for (auto cell : module->selected_cells())
if (cell->name[0] == '$')
new_cell_names[cell] = derive_name_from_cell_output_wire(cell, cell_suffix, flag_move_to_cell);
for (auto &[cell, new_name] : new_cell_names) {
if (flag_move_to_cell) {
TwineRef new_name_ref = TwineSearch(&module->design->twines).find(new_name.str());
TwineRef new_name_ref = search.find(new_name.str());
RTLIL::Wire *found_wire = new_name_ref != Twine::Null ? module->wire(new_name_ref) : nullptr;
if (found_wire) {
std::string wire_suffix = cell_suffix;
@ -462,7 +465,7 @@ struct RenamePass : public Pass {
TwineRef buf_ref;
do {
buf = stringf("\\%s%d%s", pattern_prefix, counter++, pattern_suffix);
buf_ref = TwineSearch(&module->design->twines).find(buf.str());
buf_ref = search.find(buf.str());
} while (buf_ref != Twine::Null && module->wire(buf_ref) != nullptr);
new_wire_names[wire] = buf;
}
@ -473,7 +476,7 @@ struct RenamePass : public Pass {
TwineRef buf_ref;
do {
buf = stringf("\\%s%d%s", pattern_prefix, counter++, pattern_suffix);
buf_ref = TwineSearch(&module->design->twines).find(buf.str());
buf_ref = search.find(buf.str());
} while (buf_ref != Twine::Null && module->cell(buf_ref) != nullptr);
new_cell_names[cell] = buf;
}

5
passes/cmds/setattr.cc
View file

@ -233,9 +233,10 @@ struct ChparamPass : public Pass {
break;
}
TwineSearch search(&design->twines);
for (int i = argidx; i < GetSize(args); i++)
if (design->module("$abstract\\" + args[i]) != nullptr &&
design->module(RTLIL::escape_id(args[i])) == nullptr)
if (design->module(search.find("$abstract\\" + args[i])) != nullptr &&
design->module(search.find(RTLIL::escape_id(args[i]))) == nullptr)
args[i] = "$abstract\\" + args[i];
extra_args(args, argidx, design);

3
passes/cmds/stat.cc
View file

@ -962,7 +962,8 @@ struct StatPass : public Pass {
continue;
}
if (args[argidx] == "-top" && argidx + 1 < args.size()) {
TwineRef top_ref = TwineSearch(&design->twines).find(RTLIL::escape_id(args[argidx + 1]));
TwineSearch search(&design->twines);
TwineRef top_ref = search.find(RTLIL::escape_id(args[argidx + 1]));
if (design->module(top_ref) == nullptr)
log_cmd_error("Can't find module %s.\n", args[argidx + 1]);
top_mod = design->module(top_ref);

6
passes/cmds/timeest.cc
View file

@ -420,16 +420,18 @@ struct TimeestPass : Pass {
if (select && d->selected_modules().size() > 1)
log_cmd_error("The -select option operates on a single selected module\n");
TwineSearch search(&d->twines);
for (auto m : d->selected_modules()) {
std::optional<SigBit> clk;
if (clk_domain_specified) {
if (!m->wire(TwineSearch(&m->design->twines).find(RTLIL::escape_id(clk_name)))) {
TwineRef clk_ref = search.find(RTLIL::escape_id(clk_name));
if (!m->wire(clk_ref)) {
log_warning("No domain '%s' in module %s\n", clk_name.c_str(), m);
continue;
}
clk = SigBit(m->wire(TwineSearch(&m->design->twines).find(RTLIL::escape_id(clk_name))), 0);
clk = SigBit(m->wire(clk_ref), 0);
}
EstimateSta sta(m, clk, /*top_port_endpoints=*/ !clk_domain_specified);

6
passes/cmds/viz.cc
View file

@ -706,10 +706,12 @@ struct VizWorker
IdString vg_id("\\vg");
for (auto c : module->cells())
c->attributes.erase(vg_id);
TwineSearch search(&module->design->twines);
for (auto g : graph.nodes) {
for (auto name : g->names()) {
auto w = module->wire(TwineSearch(&module->design->twines).find(name.str()));
auto c = module->cell(TwineSearch(&module->design->twines).find(name.str()));
TwineRef ref = search.find(name.str());
auto w = module->wire(ref);
auto c = module->cell(ref);
if (w) w->attributes[vg_id] = g->index;
if (c) c->attributes[vg_id] = g->index;
}

8
passes/cmds/wrapcell.cc
View file

@ -209,6 +209,7 @@ struct WrapcellPass : Pass {
for (auto cell : module->selected_cells()) {
Module *subm;
Cell *subcell;
TwineRef name_ref;
if (!ct.cell_known(cell->type_impl))
log_error("Non-internal cell type '%s' on cell '%s' in module '%s' unsupported\n",
@ -238,10 +239,11 @@ struct WrapcellPass : Pass {
cell, module);
IdString name = RTLIL::escape_id(unescaped_name.value());
if (d->module(name))
name_ref = d->twines.add(std::string{name.str()});
if (d->module(name_ref))
goto replace_cell;
subm = d->addModule(d->twines.add(Twine{name.str()}));
subm = d->addModule(name_ref);
subcell = subm->addCell(Twine{"$1"}, TwineRef(cell->type));
for (auto conn : cell->connections()) {
if (ct.cell_output(cell->type_impl, conn.first)) {
@ -294,7 +296,7 @@ struct WrapcellPass : Pass {
for (auto chunk : collect_chunks(used_outputs))
new_connections[chunk.format(cell)] = chunk.sample(cell);
cell->type_impl = cell->module->design->twines.add(Twine{name.str()});
cell->type_impl = name_ref;
cell->connections_ = new_connections;
}
}

6
passes/equiv/equiv_purge.cc
View file

@ -44,10 +44,11 @@ struct EquivPurgeWorker
}
}
TwineSearch search(&module->design->twines);
while (1)
{
std::string name = stringf("\\equiv_%d", name_cnt++);
if (module->count_id(TwineSearch(&module->design->twines).find(name)))
if (module->count_id(search.find(name)))
continue;
Wire *wire = module->addWire(Twine{name}, GetSize(sig));
@ -71,10 +72,11 @@ struct EquivPurgeWorker
}
}
TwineSearch search(&module->design->twines);
while (1)
{
std::string name = stringf("\\equiv_%d", name_cnt++);
if (module->count_id(TwineSearch(&module->design->twines).find(name)))
if (module->count_id(search.find(name)))
continue;
Wire *wire = module->addWire(Twine{name}, GetSize(sig));

4
passes/fsm/fsm_extract.cc
View file

@ -368,7 +368,7 @@ static void extract_fsm(RTLIL::Wire *wire)
// create fsm cell
RTLIL::Cell *fsm_cell = module->addCell(Twine{stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++)}, TW($fsm));
RTLIL::Cell *fsm_cell = module->addCell(Twine{stringf("$fsm$%s$%d", wire->name.str().c_str(), autoidx++)}, TW($fsm));
fsm_cell->setPort(TW::CLK, clk);
fsm_cell->setPort(TW::ARST, arst);
fsm_cell->parameters[ID::CLK_POLARITY] = clk_polarity ? State::S1 : State::S0;
@ -389,7 +389,7 @@ static void extract_fsm(RTLIL::Wire *wire)
// rename original state wire
wire->attributes.erase(ID::fsm_encoding);
module->rename(wire, module->design->twines.add(Twine{stringf("$fsm$oldstate%s", wire->name.c_str())}));
module->rename(wire, module->design->twines.add(Twine{stringf("$fsm$oldstate%s", wire->name.str().c_str())}));
if(wire->attributes.count(ID::hdlname)) {
auto hdlname = wire->get_hdlname_attribute();
hdlname.pop_back();

12
passes/hierarchy/flatten.cc
View file

@ -52,14 +52,14 @@ IdString concat_name(RTLIL::Cell *cell, IdString const &object_name, const std::
{
std::string_view object_name_view(object_name.c_str());
if (object_name_view[0] == '\\'){
return concat_views(cell->name.c_str(), separator, object_name_view.substr(1));
return concat_views(cell->name.str(), separator, object_name_view.substr(1));
}
constexpr std::string_view prefix = "$flatten";
if (object_name_view.substr(0, prefix.size()) == prefix){
object_name_view.remove_prefix(prefix.size());
}
return concat_views(prefix, cell->name.c_str(), separator, object_name_view);
return concat_views(prefix, cell->name.str(), separator, object_name_view);
}
template<class T>
@ -122,7 +122,7 @@ struct FlattenWorker
new_hdlname = cell->get_string_attribute(ID(hdlname));
} else {
log_assert(!cell->name.empty());
new_hdlname = cell->name.c_str() + 1;
new_hdlname = cell->name.unescaped();
}
new_hdlname += ' ';
@ -140,14 +140,14 @@ struct FlattenWorker
new_scopename = cell->get_string_attribute(ID(hdlname));
} else {
log_assert(!cell->name.empty());
new_scopename = cell->name.c_str() + 1;
new_scopename = cell->name.unescaped();
}
new_scopename += ' ';
new_scopename += object->get_string_attribute(ID(scopename));
object->set_string_attribute(ID(scopename), new_scopename);
} else if (create_scopename) {
log_assert(!cell->name.empty());
object->set_string_attribute(ID(scopename), cell->name.c_str() + 1);
object->set_string_attribute(ID(scopename), cell->name.unescaped());
}
}
}
@ -255,7 +255,7 @@ struct FlattenWorker
std::string port_name_str = design->twines.str(port_name);
if (!port_name_str.empty() && port_name_str[0] == '$')
log_error("Can't map port `%s' of cell `%s' to template `%s'!\n",
std::string(port_name_str).c_str(), cell->name.c_str(), design->twines.str(tpl->meta_->name).c_str());
std::string(port_name_str).c_str(), cell->name.str().c_str(), design->twines.str(tpl->meta_->name).c_str());
continue;
}

12
passes/hierarchy/hierarchy.cc
View file

@ -389,7 +389,7 @@ RTLIL::Module *get_module(RTLIL::Design &design,
const std::vector<std::string> &libdirs)
{
std::string cell_type = design.twines.str(cell.type.ref());
RTLIL::Module *abs_mod = design.module(TwineSearch(&design.twines).find("$abstract" + cell_type));
RTLIL::Module *abs_mod = design.module(design.twines.find(Twine{"$abstract" + cell_type}));
if (abs_mod) {
cell.type_impl = design.twines.add(std::string{design.twines.str(abs_mod->derive(&design, cell.parameters))});
cell.parameters.clear();
@ -741,12 +741,12 @@ int find_top_mod_score(Design *design, Module *module, dict<Module*, int> &db)
int score = 0;
db[module] = 0;
for (auto cell : module->cells()) {
std::string celltype = cell->type.str();
// Is this an array instance
if (celltype.compare(0, strlen("$array:"), "$array:") == 0)
celltype = basic_cell_type(celltype);
// Is this cell a module instance?
auto instModule = design->module(TwineSearch(&design->twines).find(celltype));
RTLIL::Module *instModule;
if (cell->type.begins_with("$array:"))
instModule = design->module(TwineSearch(&design->twines).find(basic_cell_type(cell->type.str())));
else
instModule = design->module(cell->type.ref());
// If there is no instance for this, issue a warning.
if (instModule != nullptr) {
score = max(score, find_top_mod_score(design, instModule, db) + 1);

2
passes/memory/memory_bram.cc
View file

@ -215,7 +215,7 @@ struct rules_t
{
for (const bram_t& bram : variants)
{
if (design->module(bram.name))
if (design->module(design->twines.add(std::string{bram.name.str()})))
continue;
bram.load_blackbox(design);

4
passes/memory/memory_map.cc
View file

@ -265,10 +265,10 @@ struct MemoryMapWorker
RTLIL::Wire *w_out = module->addWire(design->twines.add(Twine{w_out_name}), mem.width);
if (formal && mem.packed && mem.cell->name.c_str()[0] == '\\') {
if (formal && mem.packed && mem.cell->name.isPublic()) {
auto hdlname = mem.cell->get_hdlname_attribute();
if (hdlname.empty())
hdlname.push_back(mem.cell->name.c_str() + 1);
hdlname.push_back(mem.cell->name.unescaped());
hdlname.push_back(stringf("[%d]", addr));
w_out->set_hdlname_attribute(hdlname);
}

2
passes/opt/opt_expr.cc
View file

@ -586,8 +586,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
log("Couldn't topologically sort cells, optimizing module %s may take a longer time.\n", module);
}
log("iterating over %d cells\n", GetSize(cells.sorted));
for (auto cell : cells.sorted)
{
#define ACTION_DO(_p_, _s_) do { OptExprPatcher patcher(module, &assign_map); patcher.patch(cell, _p_, _s_, input.as_string()); goto next_cell; } while (0)

2
passes/opt/peepopt_formal_clockgateff.pmg
View file

@ -18,7 +18,7 @@ pattern formal_clockgateff
// assign gated_clk_o = flopped_en & clk_i;
state <SigSpec> clk en latched_en gated_clk
state <IdString> latched_en_port_name
state <TwineRef> latched_en_port_name
match latch
select latch->type == $dlatch

12
passes/pmgen/generate.h
View file

@ -50,12 +50,12 @@ void pmtest_addports(Module *module)
ibits.append(bit);
}
if (!ibits.empty()) {
Wire *w = module->addWire(stringf("\\i%d", icnt++), GetSize(ibits));
Wire *w = module->addWire(Twine{stringf("\\i%d", icnt++)}, GetSize(ibits));
w->port_input = true;
module->connect(ibits, w);
}
if (!obits.empty()) {
Wire *w = module->addWire(stringf("\\o%d", ocnt++), GetSize(obits));
Wire *w = module->addWire(Twine{stringf("\\o%d", ocnt++)}, GetSize(obits));
w->port_output = true;
module->connect(w, obits);
}
@ -78,7 +78,7 @@ void generate_pattern(std::function<void(pm&,std::function<void()>)> run, const
while (modcnt < maxmodcnt)
{
int submodcnt = 0, itercnt = 0, cellcnt = 0;
Module *mod = design->addModule(NEW_ID);
Module *mod = design->addModule(design->twines.add(NEW_TWINE));
while (modcnt < maxmodcnt && submodcnt < maxsubcnt && itercnt++ < 1000)
{
@ -105,8 +105,8 @@ void generate_pattern(std::function<void(pm&,std::function<void()>)> run, const
cellcnt = GetSize(mod->cells());
if (found_match) {
Module *m = design->addModule(stringf("\\pmtest_%s_%s_%05d",
pmclass, pattern, modcnt++));
Module *m = design->addModule(design->twines.add(Twine{stringf("\\pmtest_%s_%s_%05d",
pmclass, pattern, modcnt++)}));
log("Creating module %s with %d cells.\n", m, cellcnt);
mod->cloneInto(m);
pmtest_addports(m);
@ -126,7 +126,7 @@ void generate_pattern(std::function<void(pm&,std::function<void()>)> run, const
design->remove(mod);
}
Module *m = design->addModule(stringf("\\pmtest_%s_%s", pmclass, pattern));
Module *m = design->addModule(design->twines.add(Twine{stringf("\\pmtest_%s_%s", pmclass, pattern)}));
log("Creating module %s with %d cells.\n", m, GetSize(mods));
for (auto mod : mods) {
Cell *c = m->addCell(mod->name, mod->name);

2
passes/pmgen/pmgen.py
View file

@ -417,7 +417,7 @@ with open(outfile, "w") as f:
for v, n in sorted(ids.items()):
if n[0] == "\\":
print(" TwineRef {}{{TW({})}};".format(v, n[1:]), file=f)
print(" TwineRef {}{{TW::{}}};".format(v, n[1:]), file=f)
else:
print(" TwineRef {}{{TW({})}};".format(v, n), file=f)
print("", file=f)

12
passes/pmgen/test_pmgen.cc
View file

@ -37,7 +37,7 @@ void reduce_chain(test_pmgen_pm &pm)
if (ud.longest_chain.empty())
return;
log("Found chain of length %d (%s):\n", GetSize(ud.longest_chain), design->twines.unescaped_str(st.first->type));
log("Found chain of length %d (%s):\n", GetSize(ud.longest_chain), pm.module->design->twines.unescaped_str(st.first->type_impl));
SigSpec A;
SigSpec Y = ud.longest_chain.front().first->getPort(TW::Y);
@ -49,7 +49,7 @@ void reduce_chain(test_pmgen_pm &pm)
A.append(cell->getPort(TW::A));
A.append(cell->getPort(TW::B));
} else {
A.append(cell->getPort(it.second == ID::A ? ID::B : ID::A));
A.append(cell->getPort(it.second == TW::A ? TW::B : TW::A));
}
log(" %s\n", cell);
pm.autoremove(cell);
@ -66,7 +66,7 @@ void reduce_chain(test_pmgen_pm &pm)
else
log_abort();
log(" -> %s (%s)\n", c, design->twines.unescaped_str(c->type));
log(" -> %s (%s)\n", c, pm.module->design->twines.unescaped_str(c->type_impl));
}
void reduce_tree(test_pmgen_pm &pm)
@ -81,7 +81,7 @@ void reduce_tree(test_pmgen_pm &pm)
SigSpec Y = st.first->getPort(TW::Y);
pm.autoremove(st.first);
log("Found %s tree with %d leaves for %s (%s).\n", design->twines.unescaped_str(st.first->type),
log("Found %s tree with %d leaves for %s (%s).\n", pm.module->design->twines.unescaped_str(st.first->type_impl),
GetSize(A), log_signal(Y), st.first);
Cell *c;
@ -95,7 +95,7 @@ void reduce_tree(test_pmgen_pm &pm)
else
log_abort();
log(" -> %s (%s)\n", c, design->twines.unescaped_str(c->type));
log(" -> %s (%s)\n", c, pm.module->design->twines.unescaped_str(c->type_impl));
}
void opt_eqpmux(test_pmgen_pm &pm)
@ -113,7 +113,7 @@ void opt_eqpmux(test_pmgen_pm &pm)
pm.autoremove(st.pmux);
Cell *c = pm.module->addMux(NEW_TWINE, NE, EQ, st.eq->getPort(TW::Y), Y);
log(" -> %s (%s)\n", c, design->twines.unescaped_str(c->type));
log(" -> %s (%s)\n", c, pm.module->design->twines.unescaped_str(c->type_impl));
}
struct TestPmgenPass : public Pass {

6
passes/pmgen/test_pmgen.pmg
View file

@ -1,7 +1,7 @@
pattern reduce
state <IdString> portname
udata <vector<pair<Cell*, IdString>>> chain longest_chain
state <TwineRef> portname
udata <vector<pair<Cell*, TwineRef>>> chain longest_chain
udata <pool<Cell*>> non_first_cells
udata <SigSpec> leaves
@ -86,7 +86,7 @@ generate 10
SigSpec B = module->addWire(NEW_TWINE);
SigSpec Y = port(chain.back().first, chain.back().second);
Cell *c = module->addAndGate(NEW_TWINE, A, B, Y);
c->type = chain.back().first->type;
c->type_impl = chain.back().first->type_impl;
endmatch
code

3
passes/proc/proc_arst.cc
View file

@ -288,8 +288,9 @@ struct ProcArstPass : public Pass {
extra_args(args, argidx, design);
pool<Wire*> delete_initattr_wires;
TwineSearch search(&design->twines);
TwineRef global_arst_ref = global_arst.empty() ? Twine::Null
: TwineSearch(&design->twines).find(global_arst);
: search.find(global_arst);
for (auto mod : design->all_selected_modules()) {
SigMap assign_map(mod);

4
passes/proc/proc_rmdead.cc
View file

@ -154,10 +154,10 @@ struct ProcRmdeadPass : public Pass {
proc_rmdead(switch_it, counter, full_case_counter);
if (counter > 0)
log("Removed %d dead cases from process %s in module %s.\n", counter,
proc, mod);
log_id(proc), log_id(mod));
if (full_case_counter > 0)
log("Marked %d switch rules as full_case in process %s in module %s.\n",
full_case_counter, proc, mod);
full_case_counter, log_id(proc), log_id(mod));
total_counter += counter;
}
}

23
passes/sat/eval.cc
View file

@ -236,6 +236,7 @@ struct VlogHammerReporter
void run()
{
TwineSearch search(&design->twines);
for (int idx = 0; idx < int(patterns.size()); idx++)
{
log("Creating report for pattern %d: %s\n", idx, log_signal(patterns[idx]));
@ -252,7 +253,7 @@ struct VlogHammerReporter
std::vector<RTLIL::State> bits(patterns[idx].begin(), patterns[idx].begin() + total_input_width);
for (int i = 0; i < int(inputs.size()); i++) {
RTLIL::Wire *wire = module->wire(TwineSearch(&design->twines).find(inputs[i].str()));
RTLIL::Wire *wire = module->wire(search.find(inputs[i].str()));
for (int j = input_widths[i]-1; j >= 0; j--) {
ce.set(RTLIL::SigSpec(wire, j), bits.back());
recorded_set_vars.append(RTLIL::SigSpec(wire, j));
@ -304,12 +305,14 @@ struct VlogHammerReporter
VlogHammerReporter(RTLIL::Design *design, std::string module_prefix, std::string module_list, std::string input_list, std::string pattern_list) : design(design)
{
TwineSearch search(&design->twines);
for (auto name : split(module_list, ",")) {
RTLIL::IdString esc_name = RTLIL::escape_id(module_prefix + name);
if (design->module(TwineSearch(&design->twines).find(esc_name.str())) == nullptr)
RTLIL::Module *mod = design->module(search.find(esc_name.str()));
if (mod == nullptr)
log_error("Can't find module %s in current design!\n", name);
log("Using module %s (%s).\n", esc_name, name);
modules.push_back(design->module(TwineSearch(&design->twines).find(esc_name.str())));
modules.push_back(mod);
module_names.push_back(name);
}
@ -317,10 +320,11 @@ struct VlogHammerReporter
for (auto name : split(input_list, ",")) {
int width = -1;
RTLIL::IdString esc_name = RTLIL::escape_id(name);
TwineRef esc_ref = search.find(esc_name.str());
for (auto mod : modules) {
if (mod->wire(TwineSearch(&design->twines).find(esc_name.str())) == nullptr)
if (mod->wire(esc_ref) == nullptr)
log_error("Can't find input %s in module %s!\n", name, design->twines.unescaped_str(mod->name));
RTLIL::Wire *port = mod->wire(TwineSearch(&design->twines).find(esc_name.str()));
RTLIL::Wire *port = mod->wire(esc_ref);
if (!port->port_input || port->port_output)
log_error("Wire %s in module %s is not an input!\n", name, design->twines.unescaped_str(mod->name));
if (width >= 0 && width != port->width)
@ -414,11 +418,14 @@ struct EvalPass : public Pass {
/* this should only be used for regression testing of ConstEval -- see vloghammer */
std::string mod1_name = RTLIL::escape_id(args[++argidx]);
std::string mod2_name = RTLIL::escape_id(args[++argidx]);
if (design->module(TwineSearch(&design->twines).find(mod1_name)) == nullptr)
TwineSearch search(&design->twines);
RTLIL::Module *mod1 = design->module(search.find(mod1_name));
RTLIL::Module *mod2 = design->module(search.find(mod2_name));
if (mod1 == nullptr)
log_error("Can't find module `%s'!\n", mod1_name);
if (design->module(TwineSearch(&design->twines).find(mod2_name)) == nullptr)
if (mod2 == nullptr)
log_error("Can't find module `%s'!\n", mod2_name);
BruteForceEquivChecker checker(design->module(TwineSearch(&design->twines).find(mod1_name)), design->module(TwineSearch(&design->twines).find(mod2_name)), args[argidx-2] == "-brute_force_equiv_checker_x");
BruteForceEquivChecker checker(mod1, mod2, args[argidx-2] == "-brute_force_equiv_checker_x");
if (checker.errors > 0)
log_cmd_error("Modules are not equivalent!\n");
log("Verified %s = %s (using brute-force check on %d cases).\n",

77
passes/sat/expose.cc
View file

@ -29,7 +29,7 @@ struct dff_map_info_t {
RTLIL::SigSpec sig_d, sig_clk, sig_arst;
bool clk_polarity, arst_polarity;
RTLIL::Const arst_value;
std::vector<RTLIL::IdString> cells;
std::vector<TwineRef> cells;
};
struct dff_map_bit_info_t {
@ -39,18 +39,18 @@ struct dff_map_bit_info_t {
RTLIL::Cell *cell;
};
bool consider_wire(RTLIL::Wire *wire, std::map<RTLIL::IdString, dff_map_info_t> &dff_dq_map)
bool consider_wire(RTLIL::Wire *wire, std::map<TwineRef, dff_map_info_t> &dff_dq_map)
{
if (wire->name[0] == '$' || dff_dq_map.count(wire->name))
if (wire->name[0] == '$' || dff_dq_map.count(wire->name.ref()))
return false;
if (wire->port_input)
return false;
return true;
}
bool consider_cell(RTLIL::Design *design, std::set<RTLIL::IdString> &dff_cells, RTLIL::Cell *cell)
bool consider_cell(RTLIL::Design *design, std::set<TwineRef> &dff_cells, RTLIL::Cell *cell)
{
if (cell->name[0] == '$' || dff_cells.count(cell->name))
if (cell->name[0] == '$' || dff_cells.count(cell->name.ref()))
return false;
if (cell->type[0] == '\\' && (design->module(cell->type_impl) == nullptr))
return false;
@ -75,7 +75,7 @@ bool compare_cells(RTLIL::Cell *cell1, RTLIL::Cell *cell2)
return true;
}
void find_dff_wires(std::set<RTLIL::IdString> &dff_wires, RTLIL::Module *module)
void find_dff_wires(std::set<TwineRef> &dff_wires, RTLIL::Module *module)
{
CellTypes ct;
ct.setup_internals_mem();
@ -91,11 +91,11 @@ void find_dff_wires(std::set<RTLIL::IdString> &dff_wires, RTLIL::Module *module)
for (auto w : module->wires()) {
if (dffsignals.check_any(w))
dff_wires.insert(w->name);
dff_wires.insert(w->name.ref());
}
}
void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Module *module)
void create_dff_dq_map(std::map<TwineRef, dff_map_info_t> &map, RTLIL::Module *module)
{
std::map<RTLIL::SigBit, dff_map_bit_info_t> bit_info;
SigMap sigmap(module);
@ -159,7 +159,7 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Mo
}
}
std::map<RTLIL::IdString, dff_map_info_t> empty_dq_map;
std::map<TwineRef, dff_map_info_t> empty_dq_map;
for (auto w : module->wires())
{
if (!consider_wire(w, empty_dq_map))
@ -202,16 +202,17 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Mo
info.arst_polarity = ref_info.arst_polarity;
info.arst_value = arst_value;
for (auto it : cells)
info.cells.push_back(it->name);
map[w->name] = info;
info.cells.push_back(it->name.ref());
map[w->name.ref()] = info;
}
}
RTLIL::Wire *add_new_wire(RTLIL::Module *module, RTLIL::IdString name, int width = 1)
RTLIL::Wire *add_new_wire(RTLIL::Module *module, std::string name, int width = 1)
{
if (module->count_id(name))
log_error("Attempting to create wire %s, but a wire of this name exists already! Hint: Try another value for -sep.\n", design->twines.unescaped_str(name));
return module->addWire(name, width);
TwineRef ref = module->design->twines.add(std::string{name});
if (module->count_id(ref))
log_error("Attempting to create wire %s, but a wire of this name exists already! Hint: Try another value for -sep.\n", name.c_str());
return module->addWire(ref, width);
}
struct ExposePass : public Pass {
@ -311,13 +312,13 @@ struct ExposePass : public Pass {
CellTypes ct(design);
std::map<RTLIL::Module*, std::map<RTLIL::IdString, dff_map_info_t>> dff_dq_maps;
std::map<RTLIL::Module*, std::set<RTLIL::IdString>> dff_cells;
std::map<RTLIL::Module*, std::map<TwineRef, dff_map_info_t>> dff_dq_maps;
std::map<RTLIL::Module*, std::set<TwineRef>> dff_cells;
if (flag_evert_dff)
{
RTLIL::Module *first_module = NULL;
std::set<RTLIL::IdString> shared_dff_wires;
std::set<TwineRef> shared_dff_wires;
for (auto mod : design->selected_modules())
{
@ -331,7 +332,7 @@ struct ExposePass : public Pass {
shared_dff_wires.insert(it.first);
first_module = mod;
} else {
std::set<RTLIL::IdString> new_shared_dff_wires;
std::set<TwineRef> new_shared_dff_wires;
for (auto &it : shared_dff_wires) {
if (!dff_dq_maps[mod].count(it))
continue;
@ -346,7 +347,7 @@ struct ExposePass : public Pass {
if (flag_shared)
for (auto &map_it : dff_dq_maps)
{
std::map<RTLIL::IdString, dff_map_info_t> new_map;
std::map<TwineRef, dff_map_info_t> new_map;
for (auto &it : map_it.second)
if (shared_dff_wires.count(it.first))
new_map[it.first] = it.second;
@ -359,8 +360,8 @@ struct ExposePass : public Pass {
dff_cells[it1.first].insert(it3);
}
std::set<RTLIL::IdString> shared_wires, shared_cells;
std::set<RTLIL::IdString> used_names;
std::set<TwineRef> shared_wires, shared_cells;
std::set<TwineRef> used_names;
if (flag_shared)
{
@ -368,7 +369,7 @@ struct ExposePass : public Pass {
for (auto module : design->selected_modules())
{
std::set<RTLIL::IdString> dff_wires;
std::set<TwineRef> dff_wires;
if (flag_dff)
find_dff_wires(dff_wires, module);
@ -376,19 +377,19 @@ struct ExposePass : public Pass {
{
for (auto w : module->wires())
if (design->selected(module, w) && consider_wire(w, dff_dq_maps[module]))
if (!flag_dff || dff_wires.count(w->name))
shared_wires.insert(w->name);
if (!flag_dff || dff_wires.count(w->name.ref()))
shared_wires.insert(w->name.ref());
if (flag_evert)
for (auto cell : module->cells())
if (design->selected(module, cell) && consider_cell(design, dff_cells[module], cell))
shared_cells.insert(cell->name);
shared_cells.insert(cell->name.ref());
first_module = module;
}
else
{
std::vector<RTLIL::IdString> delete_shared_wires, delete_shared_cells;
std::vector<TwineRef> delete_shared_wires, delete_shared_cells;
for (auto &it : shared_wires)
{
@ -445,7 +446,7 @@ struct ExposePass : public Pass {
for (auto module : design->selected_modules())
{
std::set<RTLIL::IdString> dff_wires;
std::set<TwineRef> dff_wires;
if (flag_dff && !flag_shared)
find_dff_wires(dff_wires, module);
@ -453,17 +454,17 @@ struct ExposePass : public Pass {
SigMap out_to_in_map;
std::map<RTLIL::Wire*, RTLIL::IdString> wire_map;
std::map<RTLIL::Wire*, std::string> wire_map;
for (auto w : module->wires())
{
if (flag_shared) {
if (shared_wires.count(w->name) == 0)
if (shared_wires.count(w->name.ref()) == 0)
continue;
} else {
if (!design->selected(module, w) || !consider_wire(w, dff_dq_maps[module]))
continue;
if (flag_dff && !dff_wires.count(w->name))
if (flag_dff && !dff_wires.count(w->name.ref()))
continue;
}
@ -472,7 +473,7 @@ struct ExposePass : public Pass {
if (!w->port_input) {
w->port_input = true;
log("New module port: %s/%s\n", module, w);
wire_map[w] = NEW_ID;
wire_map[w] = NEW_ID.str();
}
}
else
@ -492,7 +493,7 @@ struct ExposePass : public Pass {
{
for (auto &wm : wire_map)
{
RTLIL::Wire *in_wire = module->addWire(wm.second, GetSize(wm.first));
RTLIL::Wire *in_wire = module->addWire(module->design->twines.add(std::string{wm.second}), GetSize(wm.first));
out_to_in_map.add(wm.first, in_wire);
}
@ -542,7 +543,7 @@ struct ExposePass : public Pass {
dff_map_info_t &info = dq.second;
RTLIL::Wire *wire_dummy_q = add_new_wire(module, NEW_ID, 0);
RTLIL::Wire *wire_dummy_q = add_new_wire(module, NEW_ID.str(), 0);
for (auto &cell_name : info.cells) {
RTLIL::Cell *cell = module->cell(cell_name);
@ -616,7 +617,7 @@ struct ExposePass : public Pass {
for (auto cell : module->cells())
{
if (flag_shared) {
if (shared_cells.count(cell->name) == 0)
if (shared_cells.count(cell->name.ref()) == 0)
continue;
} else {
if (!design->selected(module, cell) || !consider_cell(design, dff_cells[module], cell))
@ -632,7 +633,7 @@ struct ExposePass : public Pass {
if (!p->port_input && !p->port_output)
continue;
RTLIL::Wire *w = add_new_wire(module, cell->name.str() + sep + design->twines.unescaped_str(p->name), p->width);
RTLIL::Wire *w = add_new_wire(module, cell->name.str() + sep + design->twines.unescaped_str(p->name.ref()), p->width);
if (p->port_input)
w->port_output = true;
if (p->port_output)
@ -641,8 +642,8 @@ struct ExposePass : public Pass {
log("New module port: %s/%s (%s)\n", module, w, cell->type.unescaped());
RTLIL::SigSpec sig;
if (cell->hasPort(p->name))
sig = cell->getPort(p->name);
if (cell->hasPort(p->name.ref()))
sig = cell->getPort(p->name.ref());
sig.extend_u0(w->width);
if (w->port_input)
module->connect(RTLIL::SigSig(sig, w));

36
passes/sat/fmcombine.cc
View file

@ -40,11 +40,11 @@ struct FmcombineWorker
Design *design;
Module *original = nullptr;
Module *module = nullptr;
IdString orig_type, combined_type;
TwineRef orig_type, combined_type;
FmcombineWorker(Design *design, IdString orig_type, const opts_t &opts) :
FmcombineWorker(Design *design, TwineRef orig_type, const opts_t &opts) :
opts(opts), design(design), original(design->module(orig_type)),
orig_type(orig_type), combined_type(stringf("$fmcombine%s", orig_type))
orig_type(orig_type), combined_type(design->twines.add(stringf("$fmcombine%s", design->twines.str(orig_type).c_str())))
{
}
@ -53,7 +53,7 @@ struct FmcombineWorker
SigSpec newsig;
for (auto chunk : sig.chunks()) {
if (chunk.wire != nullptr)
chunk.wire = module->wire(chunk.wire->name.str() + suffix);
chunk.wire = module->wire(design->twines.add(std::string{chunk.wire->name.str() + suffix}));
newsig.append(chunk);
}
return newsig;
@ -61,7 +61,7 @@ struct FmcombineWorker
Cell *import_prim_cell(Cell *cell, const string &suffix)
{
Cell *c = module->addCell(cell->name.str() + suffix, cell->type);
Cell *c = module->addCell(Twine{cell->name.str() + suffix}, cell->type_impl);
c->parameters = cell->parameters;
c->attributes = cell->attributes;
@ -79,16 +79,16 @@ struct FmcombineWorker
if (!cell->parameters.empty())
log_cmd_error("Cell %s.%s has unresolved instance parameters.\n", original, cell);
FmcombineWorker sub_worker(design, cell->type, opts);
FmcombineWorker sub_worker(design, cell->type_impl, opts);
sub_worker.generate();
Cell *c = module->addCell(cell->name.str() + "_combined", sub_worker.combined_type);
Cell *c = module->addCell(Twine{cell->name.str() + "_combined"}, sub_worker.combined_type);
// c->parameters = cell->parameters;
c->attributes = cell->attributes;
for (auto &conn : cell->connections()) {
c->setPort(conn.first.str() + "_gold", import_sig(conn.second, "_gold"));
c->setPort(conn.first.str() + "_gate", import_sig(conn.second, "_gate"));
c->setPort(design->twines.add(std::string{design->twines.str(conn.first) + "_gold"}), import_sig(conn.second, "_gold"));
c->setPort(design->twines.add(std::string{design->twines.str(conn.first) + "_gate"}), import_sig(conn.second, "_gate"));
}
}
@ -103,8 +103,8 @@ struct FmcombineWorker
module = design->addModule(combined_type);
for (auto wire : original->wires()) {
module->addWire(wire->name.str() + "_gold", wire);
module->addWire(wire->name.str() + "_gate", wire);
module->addWire(Twine{wire->name.str() + "_gold"}, wire);
module->addWire(Twine{wire->name.str() + "_gate"}, wire);
}
module->fixup_ports();
@ -326,9 +326,9 @@ struct FmcombinePass : public Pass {
}
else if (argidx+3 == args.size())
{
IdString module_name = RTLIL::escape_id(args[argidx++]);
IdString gold_name = RTLIL::escape_id(args[argidx++]);
IdString gate_name = RTLIL::escape_id(args[argidx++]);
TwineRef module_name = design->twines.add(RTLIL::escape_id(args[argidx++]));
TwineRef gold_name = design->twines.add(RTLIL::escape_id(args[argidx++]));
TwineRef gate_name = design->twines.add(RTLIL::escape_id(args[argidx++]));
module = design->module(module_name);
if (module == nullptr)
@ -361,9 +361,9 @@ struct FmcombinePass : public Pass {
if (!gate_cell->parameters.empty())
log_cmd_error("Gate cell has unresolved instance parameters.\n");
FmcombineWorker worker(design, gold_cell->type, opts);
FmcombineWorker worker(design, gold_cell->type_impl, opts);
worker.generate();
IdString combined_cell_name = module->uniquify(stringf("\\%s_%s", gold_cell, gate_cell));
TwineRef combined_cell_name = module->uniquify(Twine{stringf("\\%s_%s", gold_cell, gate_cell)});
Cell *cell = module->addCell(combined_cell_name, worker.combined_type);
cell->attributes = gold_cell->attributes;
@ -372,11 +372,11 @@ struct FmcombinePass : public Pass {
log("Combining cells %s and %s in module %s into new cell %s.\n", gold_cell, gate_cell, module, cell);
for (auto &conn : gold_cell->connections())
cell->setPort(conn.first.str() + "_gold", conn.second);
cell->setPort(design->twines.add(std::string{design->twines.str(conn.first) + "_gold"}), conn.second);
module->remove(gold_cell);
for (auto &conn : gate_cell->connections())
cell->setPort(conn.first.str() + "_gate", conn.second);
cell->setPort(design->twines.add(std::string{design->twines.str(conn.first) + "_gate"}), conn.second);
module->remove(gate_cell);
}
} FmcombinePass;

5
passes/sat/formalff.cc
View file

@ -328,12 +328,13 @@ struct ReplacedPort {
struct HierarchyWorker
{
Design *design;
TwineSearch search;
pool<Module *> pending;
dict<Module *, std::vector<ReplacedPort>> replaced_clk_inputs;
HierarchyWorker(Design *design) :
design(design)
design(design), search(&design->twines)
{
for (auto module : design->modules())
pending.insert(module);
@ -462,7 +463,7 @@ const std::vector<ReplacedPort> &HierarchyWorker::find_replaced_clk_inputs(IdStr
if (!cell_type.isPublic())
return empty;
Module *module = design->module(TwineSearch(&design->twines).find(cell_type.str()));
Module *module = design->module(search.find(cell_type.str()));
if (module == nullptr)
return empty;

116
passes/sat/mutate.cc
View file

@ -27,8 +27,8 @@ PRIVATE_NAMESPACE_BEGIN
struct mutate_t {
string mode;
pool<string> src;
IdString module, cell;
IdString port, wire;
TwineRef module = Twine::Null, cell = Twine::Null;
TwineRef port = Twine::Null, wire = Twine::Null;
int portbit = -1;
int ctrlbit = -1;
int wirebit = -1;
@ -39,12 +39,12 @@ struct mutate_opts_t {
int seed = 0;
std::string mode;
pool<string> src;
IdString module, cell, port, wire;
TwineRef module = Twine::Null, cell = Twine::Null, port = Twine::Null, wire = Twine::Null;
int portbit = -1;
int ctrlbit = -1;
int wirebit = -1;
IdString ctrl_name;
TwineRef ctrl_name = Twine::Null;
int ctrl_width = -1, ctrl_value = -1;
bool none = false;
@ -79,13 +79,13 @@ void database_add(std::vector<mutate_t> &database, const mutate_opts_t &opts, co
return;
}
if (!opts.module.empty() && opts.module != entry.module)
if (opts.module != Twine::Null && opts.module != entry.module)
return;
if (!opts.cell.empty() && opts.cell != entry.cell)
if (opts.cell != Twine::Null && opts.cell != entry.cell)
return;
if (!opts.port.empty() && opts.port != entry.port)
if (opts.port != Twine::Null && opts.port != entry.port)
return;
if (opts.portbit >= 0 && opts.portbit != entry.portbit)
@ -94,7 +94,7 @@ void database_add(std::vector<mutate_t> &database, const mutate_opts_t &opts, co
if (opts.ctrlbit >= 0 && opts.ctrlbit != entry.ctrlbit)
return;
if (!opts.wire.empty() && opts.wire != entry.wire)
if (opts.wire != Twine::Null && opts.wire != entry.wire)
return;
if (opts.wirebit >= 0 && opts.wirebit != entry.wirebit)
@ -139,13 +139,13 @@ struct xs128_t
struct coverdb_t
{
dict<string, int> src_db;
dict<tuple<IdString, IdString>, int> wire_db;
dict<tuple<IdString, IdString, int>, int> wirebit_db;
dict<tuple<TwineRef, TwineRef>, int> wire_db;
dict<tuple<TwineRef, TwineRef, int>, int> wirebit_db;
void insert(const mutate_t &m) {
if (!m.wire.empty()) {
wire_db[tuple<IdString, IdString>(m.module, m.wire)] = 0;
wirebit_db[tuple<IdString, IdString, int>(m.module, m.wire, m.wirebit)] = 0;
if (m.wire != Twine::Null) {
wire_db[tuple<TwineRef, TwineRef>(m.module, m.wire)] = 0;
wirebit_db[tuple<TwineRef, TwineRef, int>(m.module, m.wire, m.wirebit)] = 0;
}
for (auto &s : m.src) {
src_db[s] = 0;
@ -153,9 +153,9 @@ struct coverdb_t
}
void update(const mutate_t &m) {
if (!m.wire.empty()) {
wire_db.at(tuple<IdString, IdString>(m.module, m.wire))++;
wirebit_db.at(tuple<IdString, IdString, int>(m.module, m.wire, m.wirebit))++;
if (m.wire != Twine::Null) {
wire_db.at(tuple<TwineRef, TwineRef>(m.module, m.wire))++;
wirebit_db.at(tuple<TwineRef, TwineRef, int>(m.module, m.wire, m.wirebit))++;
}
for (auto &s : m.src) {
src_db.at(s)++;
@ -164,9 +164,9 @@ struct coverdb_t
int score(const mutate_t &m) {
int this_score = m.src.empty() ? 0 : 1;
if (!m.wire.empty()) {
this_score += wire_db.at(tuple<IdString, IdString>(m.module, m.wire)) ? 0 : 5;
this_score += wirebit_db.at(tuple<IdString, IdString, int>(m.module, m.wire, m.wirebit)) ? 0 : 1;
if (m.wire != Twine::Null) {
this_score += wire_db.at(tuple<TwineRef, TwineRef>(m.module, m.wire)) ? 0 : 5;
this_score += wirebit_db.at(tuple<TwineRef, TwineRef, int>(m.module, m.wire, m.wirebit)) ? 0 : 1;
}
for (auto &s : m.src) {
this_score += src_db.at(s) ? 0 : 5;
@ -279,28 +279,28 @@ void database_reduce(std::vector<mutate_t> &database, const mutate_opts_t &opts,
if (N >= GetSize(database))
return;
mutate_once_queue_t<tuple<IdString, IdString>, mutate_queue_t> primary_queue_wire;
mutate_once_queue_t<tuple<IdString, IdString, int>, mutate_queue_t> primary_queue_bit;
mutate_once_queue_t<tuple<IdString, IdString>, mutate_queue_t> primary_queue_cell;
mutate_once_queue_t<tuple<TwineRef, TwineRef>, mutate_queue_t> primary_queue_wire;
mutate_once_queue_t<tuple<TwineRef, TwineRef, int>, mutate_queue_t> primary_queue_bit;
mutate_once_queue_t<tuple<TwineRef, TwineRef>, mutate_queue_t> primary_queue_cell;
mutate_once_queue_t<string, mutate_queue_t> primary_queue_src;
mutate_chain_queue_t<IdString, mutate_once_queue_t<IdString, mutate_queue_t>> primary_queue_module_wire;
mutate_chain_queue_t<IdString, mutate_once_queue_t<pair<IdString, int>, mutate_queue_t>> primary_queue_module_bit;
mutate_chain_queue_t<IdString, mutate_once_queue_t<IdString, mutate_queue_t>> primary_queue_module_cell;
mutate_chain_queue_t<IdString, mutate_once_queue_t<string, mutate_queue_t>> primary_queue_module_src;
mutate_chain_queue_t<TwineRef, mutate_once_queue_t<TwineRef, mutate_queue_t>> primary_queue_module_wire;
mutate_chain_queue_t<TwineRef, mutate_once_queue_t<pair<TwineRef, int>, mutate_queue_t>> primary_queue_module_bit;
mutate_chain_queue_t<TwineRef, mutate_once_queue_t<TwineRef, mutate_queue_t>> primary_queue_module_cell;
mutate_chain_queue_t<TwineRef, mutate_once_queue_t<string, mutate_queue_t>> primary_queue_module_src;
for (auto &m : database)
{
coverdb.insert(m);
if (!m.wire.empty()) {
primary_queue_wire.add(&m, tuple<IdString, IdString>(m.module, m.wire));
primary_queue_bit.add(&m, tuple<IdString, IdString, int>(m.module, m.wire, m.wirebit));
if (m.wire != Twine::Null) {
primary_queue_wire.add(&m, tuple<TwineRef, TwineRef>(m.module, m.wire));
primary_queue_bit.add(&m, tuple<TwineRef, TwineRef, int>(m.module, m.wire, m.wirebit));
primary_queue_module_wire.add(&m, m.module, m.wire);
primary_queue_module_bit.add(&m, m.module, pair<IdString, int>(m.wire, m.wirebit));
primary_queue_module_bit.add(&m, m.module, pair<TwineRef, int>(m.wire, m.wirebit));
}
primary_queue_cell.add(&m, tuple<IdString, IdString>(m.module, m.cell));
primary_queue_cell.add(&m, tuple<TwineRef, TwineRef>(m.module, m.cell));
primary_queue_module_cell.add(&m, m.module, m.cell);
for (auto &s : m.src) {
@ -433,7 +433,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
for (auto module : design->selected_modules())
{
if (!opts.module.empty() && module->name != opts.module)
if (opts.module != Twine::Null && module->name.ref() != opts.module)
continue;
SigMap sigmap(module);
@ -478,15 +478,15 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
for (auto cell : module->selected_cells())
{
if (!opts.cell.empty() && cell->name != opts.cell)
if (opts.cell != Twine::Null && cell->name.ref() != opts.cell)
continue;
for (auto &conn : cell->connections())
{
for (int i = 0; i < GetSize(conn.second); i++) {
mutate_t entry;
entry.module = module->name;
entry.cell = cell->name;
entry.module = module->name.ref();
entry.cell = cell->name.ref();
entry.port = conn.first;
entry.portbit = i;
@ -497,7 +497,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
if (bit.wire && bit.wire->name.isPublic() && (cell->output(conn.first) || bit_user_cnt[bit] == 1)) {
for (auto &s : design->src_leaves(bit.wire))
entry.src.insert(s);
entry.wire = bit.wire->name;
entry.wire = bit.wire->name.ref();
entry.wirebit = bit.offset;
}
@ -557,7 +557,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
if (opts.none) {
string str = "mutate";
if (!opts.ctrl_name.empty())
if (opts.ctrl_name != Twine::Null)
str += stringf(" -ctrl %s %d %d", design->twines.unescaped_str(opts.ctrl_name), opts.ctrl_width, ctrl_value++);
str += " -mode none";
if (filename.empty())
@ -568,20 +568,20 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
for (auto &entry : database) {
string str = "mutate";
if (!opts.ctrl_name.empty())
if (opts.ctrl_name != Twine::Null)
str += stringf(" -ctrl %s %d %d", design->twines.unescaped_str(opts.ctrl_name), opts.ctrl_width, ctrl_value++);
str += stringf(" -mode %s", entry.mode);
if (!entry.module.empty())
if (entry.module != Twine::Null)
str += stringf(" -module %s", design->twines.unescaped_str(entry.module));
if (!entry.cell.empty())
if (entry.cell != Twine::Null)
str += stringf(" -cell %s", design->twines.unescaped_str(entry.cell));
if (!entry.port.empty())
if (entry.port != Twine::Null)
str += stringf(" -port %s", design->twines.unescaped_str(entry.port));
if (entry.portbit >= 0)
str += stringf(" -portbit %d", entry.portbit);
if (entry.ctrlbit >= 0)
str += stringf(" -ctrlbit %d", entry.ctrlbit);
if (!entry.wire.empty())
if (entry.wire != Twine::Null)
str += stringf(" -wire %s", design->twines.unescaped_str(entry.wire));
if (entry.wirebit >= 0)
str += stringf(" -wirebit %d", entry.wirebit);
@ -594,13 +594,13 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
}
}
SigSpec mutate_ctrl_sig(Module *module, IdString name, int width)
SigSpec mutate_ctrl_sig(Module *module, TwineRef name, int width)
{
Wire *ctrl_wire = module->wire(name);
if (ctrl_wire == nullptr)
{
log("Adding ctrl port %s to module %s.\n", design->twines.unescaped_str(name), module);
log("Adding ctrl port %s to module %s.\n", module->design->twines.unescaped_str(name), module);
ctrl_wire = module->addWire(name, width);
ctrl_wire->port_input = true;
@ -609,7 +609,7 @@ SigSpec mutate_ctrl_sig(Module *module, IdString name, int width)
for (auto mod : module->design->modules())
for (auto cell : mod->cells())
{
if (cell->type != module->name)
if (cell->type_impl != module->name.ref())
continue;
SigSpec ctrl = mutate_ctrl_sig(mod, name, width);
@ -625,7 +625,7 @@ SigSpec mutate_ctrl_sig(Module *module, IdString name, int width)
SigBit mutate_ctrl(Module *module, const mutate_opts_t &opts)
{
if (opts.ctrl_name.empty())
if (opts.ctrl_name == Twine::Null)
return State::S1;
SigSpec sig = mutate_ctrl_sig(module, opts.ctrl_name, opts.ctrl_width);
@ -710,14 +710,14 @@ void mutate_cnot(Design *design, const mutate_opts_t &opts, bool one)
if (cell->input(opts.port))
{
log("Add input cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, module, cell, design->twines.unescaped_str(opts.port), opts.portbit, opts.ctrlbit);
SigBit outbit = one ? module->Xor(NEW_ID, bit, ctrl) : module->Xnor(NEW_TWINE, bit, ctrl);
SigBit outbit = one ? module->Xor(NEW_TWINE, bit, ctrl) : module->Xnor(NEW_TWINE, bit, ctrl);
bit = mutate_ctrl_mux(module, opts, bit, outbit);
}
else
{
log("Add output cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, module, cell, design->twines.unescaped_str(opts.port), opts.portbit, opts.ctrlbit);
SigBit inbit = module->addWire(NEW_TWINE);
SigBit outbit = one ? module->Xor(NEW_ID, inbit, ctrl) : module->Xnor(NEW_TWINE, inbit, ctrl);
SigBit outbit = one ? module->Xor(NEW_TWINE, inbit, ctrl) : module->Xnor(NEW_TWINE, inbit, ctrl);
module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit));
bit = inbit;
}
@ -835,21 +835,21 @@ struct MutatePass : public Pass {
continue;
}
if (args[argidx] == "-ctrl" && argidx+3 < args.size()) {
opts.ctrl_name = RTLIL::escape_id(args[++argidx]);
opts.ctrl_name = design->twines.add(RTLIL::escape_id(args[++argidx]));
opts.ctrl_width = atoi(args[++argidx].c_str());
opts.ctrl_value = atoi(args[++argidx].c_str());
continue;
}
if (args[argidx] == "-module" && argidx+1 < args.size()) {
opts.module = RTLIL::escape_id(args[++argidx]);
opts.module = design->twines.add(RTLIL::escape_id(args[++argidx]));
continue;
}
if (args[argidx] == "-cell" && argidx+1 < args.size()) {
opts.cell = RTLIL::escape_id(args[++argidx]);
opts.cell = design->twines.add(RTLIL::escape_id(args[++argidx]));
continue;
}
if (args[argidx] == "-port" && argidx+1 < args.size()) {
opts.port = RTLIL::escape_id(args[++argidx]);
opts.port = design->twines.add(RTLIL::escape_id(args[++argidx]));
continue;
}
if (args[argidx] == "-portbit" && argidx+1 < args.size()) {
@ -861,7 +861,7 @@ struct MutatePass : public Pass {
continue;
}
if (args[argidx] == "-wire" && argidx+1 < args.size()) {
opts.wire = RTLIL::escape_id(args[++argidx]);
opts.wire = design->twines.add(RTLIL::escape_id(args[++argidx]));
continue;
}
if (args[argidx] == "-wirebit" && argidx+1 < args.size()) {
@ -934,29 +934,29 @@ struct MutatePass : public Pass {
}
if (opts.mode == "none") {
if (!opts.ctrl_name.empty()) {
Module *topmod = opts.module.empty() ? design->top_module() : design->module(opts.module);
if (opts.ctrl_name != Twine::Null) {
Module *topmod = opts.module == Twine::Null ? design->top_module() : design->module(opts.module);
if (topmod)
mutate_ctrl_sig(topmod, opts.ctrl_name, opts.ctrl_width);
}
return;
}
if (opts.module.empty())
if (opts.module == Twine::Null)
log_cmd_error("Missing -module argument.\n");
Module *module = design->module(opts.module);
if (module == nullptr)
log_cmd_error("Module %s not found.\n", design->twines.unescaped_str(opts.module));
if (opts.cell.empty())
if (opts.cell == Twine::Null)
log_cmd_error("Missing -cell argument.\n");
Cell *cell = module->cell(opts.cell);
if (cell == nullptr)
log_cmd_error("Cell %s not found in module %s.\n", design->twines.unescaped_str(opts.cell), design->twines.unescaped_str(opts.module));
if (opts.port.empty())
if (opts.port == Twine::Null)
log_cmd_error("Missing -port argument.\n");
if (!cell->hasPort(opts.port))

52
passes/sat/qbfsat.cc
View file

@ -47,9 +47,9 @@ pool<std::string> validate_design_and_get_inputs(RTLIL::Module *module, bool ass
found_1bit_output = true;
}
for (auto cell : module->cells()) {
if (cell->type == "$allconst")
if (cell->type == TW($allconst))
found_input = true;
if (cell->type == "$anyconst")
if (cell->type == TW($anyconst))
found_hole = true;
if (cell->type.in("$assert", "$assume"))
found_assert_assume = true;
@ -74,7 +74,7 @@ void specialize_from_file(RTLIL::Module *module, const std::string &file) {
dict<RTLIL::SigBit, RTLIL::State> hole_assignments;
for (auto cell : module->cells())
if (cell->type == "$anyconst")
if (cell->type == TW($anyconst))
anyconst_loc_to_cell[module->design->src_leaves(cell)] = cell;
std::ifstream fin(file.c_str());
@ -82,6 +82,7 @@ void specialize_from_file(RTLIL::Module *module, const std::string &file) {
log_cmd_error("could not read solution file.\n");
std::string buf;
TwineSearch search(&module->design->twines);
while (std::getline(fin, buf)) {
bool bit_assn = true;
if (!std::regex_search(buf, bit_m, hole_bit_assn_regex)) {
@ -100,8 +101,8 @@ void specialize_from_file(RTLIL::Module *module, const std::string &file) {
//We have two options to identify holes. First, try to match wire names. If we can't find a matching wire,
//then try to find a cell with a matching location.
RTLIL::SigBit hole_sigbit;
if (module->wire(hole_name) != nullptr) {
RTLIL::Wire *hole_wire = module->wire(hole_name);
if (module->wire(search.find(hole_name)) != nullptr) {
RTLIL::Wire *hole_wire = module->wire(search.find(hole_name));
hole_sigbit = RTLIL::SigSpec(hole_wire)[hole_offset];
} else {
auto locs = split_tokens(hole_loc, "|");
@ -131,7 +132,7 @@ void specialize(RTLIL::Module *module, const QbfSolutionType &sol, bool quiet =
auto hole_loc_idx_to_sigbit = sol.get_hole_loc_idx_sigbit_map(module);
pool<RTLIL::Cell *> anyconsts_to_remove;
for (auto cell : module->cells())
if (cell->type == "$anyconst")
if (cell->type == TW($anyconst))
if (hole_loc_idx_to_sigbit.find(std::make_pair(module->design->src_leaves(cell), 0)) != hole_loc_idx_to_sigbit.end())
anyconsts_to_remove.insert(cell);
for (auto cell : anyconsts_to_remove)
@ -159,11 +160,12 @@ void specialize(RTLIL::Module *module, const QbfSolutionType &sol, bool quiet =
}
void allconstify_inputs(RTLIL::Module *module, const pool<std::string> &input_wires) {
TwineSearch search(&module->design->twines);
for (auto &n : input_wires) {
RTLIL::Wire *input = module->wire(n);
RTLIL::Wire *input = module->wire(search.find(n));
log_assert(input != nullptr);
RTLIL::Cell *allconst = module->addCell("$allconst$" + n, "$allconst");
RTLIL::Cell *allconst = module->addCell(Twine{"$allconst$" + n}, TW($allconst));
allconst->setParam(ID(WIDTH), input->width);
allconst->setPort(TW::Y, input);
allconst->adopt_src_from(input);
@ -190,7 +192,7 @@ void assume_miter_outputs(RTLIL::Module *module, bool assume_neg) {
if (assume_neg) {
for (unsigned int i = 0; i < wires_to_assume.size(); ++i) {
RTLIL::SigSpec n_wire = module->LogicNot(wires_to_assume[i]->name.str() + "__n__qbfsat", wires_to_assume[i], false, wires_to_assume[i]->src_ref());
RTLIL::SigSpec n_wire = module->LogicNot(Twine{wires_to_assume[i]->name.str() + "__n__qbfsat"}, wires_to_assume[i], false, wires_to_assume[i]->src_ref());
wires_to_assume[i] = n_wire.as_wire();
}
}
@ -199,8 +201,8 @@ void assume_miter_outputs(RTLIL::Module *module, bool assume_neg) {
std::vector<RTLIL::Wire *> buf;
for (auto j = 0; j + 1 < GetSize(wires_to_assume); j += 2) {
std::stringstream strstr; strstr << i << "_" << j;
RTLIL::Wire *and_wire = module->addWire("\\_qbfsat_and_" + strstr.str(), 1);
module->addLogicAnd("$_qbfsat_and_" + strstr.str(), wires_to_assume[j], wires_to_assume[j+1], and_wire, false, wires_to_assume[j]->src_ref());
RTLIL::Wire *and_wire = module->addWire(Twine{"\\_qbfsat_and_" + strstr.str()}, 1);
module->addLogicAnd(Twine{"$_qbfsat_and_" + strstr.str()}, wires_to_assume[j], wires_to_assume[j+1], and_wire, false, wires_to_assume[j]->src_ref());
buf.push_back(and_wire);
}
if (wires_to_assume.size() % 2 == 1)
@ -209,7 +211,7 @@ void assume_miter_outputs(RTLIL::Module *module, bool assume_neg) {
}
log_assert(wires_to_assume.size() == 1);
module->addAssume("$assume_qbfsat_miter_outputs", wires_to_assume[0], RTLIL::S1);
module->addAssume(Twine{"$assume_qbfsat_miter_outputs"}, wires_to_assume[0], RTLIL::S1);
}
QbfSolutionType call_qbf_solver(RTLIL::Module *mod, const QbfSolveOptions &opt, const std::string &tempdir_name, const bool quiet = false, const int iter_num = 0) {
@ -255,8 +257,8 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) {
const std::string tempdir_name = make_temp_dir(get_base_tmpdir() + "/yosys-qbfsat-XXXXXX");
RTLIL::Module *module = mod;
RTLIL::Design *design = module->design;
std::string module_name = module->name.str();
RTLIL::IdString wire_to_optimize_name = "";
TwineRef module_name = module->name.ref();
TwineRef wire_to_optimize_name = Twine::Null;
bool maximize = false;
log_assert(module->design != nullptr);
@ -271,7 +273,7 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) {
//Find the wire to be optimized, if any:
for (auto wire : module->wires()) {
if (wire->get_bool_attribute("\\maximize") || wire->get_bool_attribute("\\minimize")) {
wire_to_optimize_name = wire->name;
wire_to_optimize_name = wire->name.ref();
maximize = wire->get_bool_attribute("\\maximize");
if (opt.nooptimize) {
if (maximize)
@ -292,7 +294,7 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) {
Pass::call(module->design, "opt");
}
if (opt.nobisection || opt.nooptimize || wire_to_optimize_name == "") {
if (opt.nobisection || opt.nooptimize || wire_to_optimize_name == Twine::Null) {
ret = call_qbf_solver(module, opt, tempdir_name, false, 0);
} else {
//Do the iterated bisection method:
@ -301,9 +303,9 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) {
unsigned int failure = 0;
unsigned int cur_thresh = 0;
log_assert(wire_to_optimize_name != "");
log_assert(wire_to_optimize_name != Twine::Null);
log_assert(module->wire(wire_to_optimize_name) != nullptr);
log("%s wire \"%s\".\n", (maximize? "Maximizing" : "Minimizing"), wire_to_optimize_name);
log("%s wire \"%s\".\n", (maximize? "Maximizing" : "Minimizing"), design->twines.str(wire_to_optimize_name));
//If maximizing, grow until we get a failure. Then bisect success and failure.
while (failure == 0 || difference(success, failure) > 1) {
@ -315,8 +317,8 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) {
RTLIL::SigSpec comparator = maximize? module->Ge(NEW_TWINE, module->wire(wire_to_optimize_name), RTLIL::Const(cur_thresh), false)
: module->Le(NEW_TWINE, module->wire(wire_to_optimize_name), RTLIL::Const(cur_thresh), false);
module->addAssume(wire_to_optimize_name.str() + "__threshold", comparator, RTLIL::Const(1, 1));
log("Trying to solve with %s %s %d.\n", wire_to_optimize_name, (maximize? ">=" : "<="), cur_thresh);
module->addAssume(Twine{design->twines.str(wire_to_optimize_name) + "__threshold"}, comparator, RTLIL::Const(1, 1));
log("Trying to solve with %s %s %d.\n", design->twines.str(wire_to_optimize_name), (maximize? ">=" : "<="), cur_thresh);
}
ret = call_qbf_solver(module, opt, tempdir_name, false, iter_num);
@ -328,7 +330,7 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) {
specialize(module, ret, true);
RTLIL::SigSpec wire, value, undef;
RTLIL::SigSpec::parse_sel(wire, design, module, wire_to_optimize_name.str());
RTLIL::SigSpec::parse_sel(wire, design, module, design->twines.str(wire_to_optimize_name));
ConstEval ce(module);
value = wire;
@ -337,7 +339,7 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) {
log_assert(value.is_fully_const());
success = value.as_const().as_int();
best_soln = ret;
log("Problem is satisfiable with %s = %d.\n", wire_to_optimize_name, success);
log("Problem is satisfiable with %s = %d.\n", design->twines.str(wire_to_optimize_name), success);
Pass::call(design, "design -pop");
module = design->module(module_name);
@ -355,7 +357,7 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) {
break;
}
else
log("Problem is NOT satisfiable with %s %s %d.\n", wire_to_optimize_name, (maximize? ">=" : "<="), failure);
log("Problem is NOT satisfiable with %s %s %d.\n", design->twines.str(wire_to_optimize_name), (maximize? ">=" : "<="), failure);
}
iter_num++;
@ -367,7 +369,7 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) {
cur_thresh = (success + failure) / 2; //bisection
}
if (success != 0 || failure != 0) {
log("Wire %s is %s at %d.\n", wire_to_optimize_name, (maximize? "maximized" : "minimized"), success);
log("Wire %s is %s at %d.\n", design->twines.str(wire_to_optimize_name), (maximize? "maximized" : "minimized"), success);
ret = best_soln;
}
}
@ -606,7 +608,7 @@ struct QbfSatPass : public Pass {
log_push();
if (!opt.specialize_from_file) {
//Save the design to restore after modiyfing the current module.
std::string module_name = module->name.str();
TwineRef module_name = module->name.ref();
QbfSolutionType ret = qbf_solve(module, opt);
module = design->module(module_name);

42
passes/sat/recover_names.cc
View file

@ -42,8 +42,8 @@ PRIVATE_NAMESPACE_BEGIN
// Similar to a SigBit; but module-independent
struct IdBit {
IdBit() : name(), bit(0) {};
IdBit(IdString name, int bit = 0) : name(name), bit(bit) {};
IdBit() : name(Twine::Null), bit(0) {};
IdBit(TwineRef name, int bit = 0) : name(name), bit(bit) {};
bool operator==(const IdBit &other) const { return name == other.name && bit == other.bit; };
bool operator!=(const IdBit &other) const { return name != other.name || bit != other.bit; };
@ -54,7 +54,7 @@ struct IdBit {
return h;
}
IdString name;
TwineRef name;
int bit;
};
@ -95,7 +95,7 @@ struct RecoverModuleWorker {
{
// Create a derivative of the module with whiteboxes flattened so we can
// run eval and sat on it
flat = design->addModule(NEW_ID);
flat = design->addModule(design->twines.add(NEW_TWINE));
mod->cloneInto(flat);
Pass::call_on_module(design, flat, "flatten -wb");
ce = new ConstEval(flat);
@ -103,7 +103,7 @@ struct RecoverModuleWorker {
// Create a mapping from primary name-bit in the box-flattened module to original sigbit
SigMap orig_sigmap(mod);
for (auto wire : mod->wires()) {
Wire *flat_wire = flat->wire(wire->name);
Wire *flat_wire = flat->wire(wire->name.ref());
if (!flat_wire)
continue;
for (int i = 0; i < wire->width; i++) {
@ -111,7 +111,7 @@ struct RecoverModuleWorker {
SigBit flat_sigbit = (*sigmap)(SigBit(flat_wire, i));
if (!orig_sigbit.wire || !flat_sigbit.wire)
continue;
flat2orig[IdBit(flat_sigbit.wire->name, flat_sigbit.offset)] = orig_sigbit;
flat2orig[IdBit(flat_sigbit.wire->name.ref(), flat_sigbit.offset)] = orig_sigbit;
}
}
find_driven_bits();
@ -127,7 +127,7 @@ struct RecoverModuleWorker {
SigBit bit(wire, i);
bit = (*sigmap)(bit);
if (bit.wire)
bit2driver[IdBit(bit.wire->name, bit.offset)] = nullptr;
bit2driver[IdBit(bit.wire->name.ref(), bit.offset)] = nullptr;
}
}
// Add cell outputs
@ -138,7 +138,7 @@ struct RecoverModuleWorker {
for (auto bit : conn.second) {
auto resolved = (*sigmap)(bit);
if (resolved.wire)
bit2driver[IdBit(resolved.wire->name, resolved.offset)] = cell;
bit2driver[IdBit(resolved.wire->name.ref(), resolved.offset)] = cell;
}
}
}
@ -148,7 +148,7 @@ struct RecoverModuleWorker {
SigBit bit(wire, i);
bit = (*sigmap)(bit);
if (bit.wire)
bit2primary[IdBit(wire->name, i)] = IdBit(bit.wire->name, bit.offset);
bit2primary[IdBit(wire->name.ref(), i)] = IdBit(bit.wire->name.ref(), bit.offset);
}
}
}
@ -215,7 +215,7 @@ struct RecoverModuleWorker {
for (auto bit : (*sigmap)(conn.second)) {
if (!bit.wire)
continue;
IdBit idbit(bit.wire->name, bit.offset);
IdBit idbit(bit.wire->name.ref(), bit.offset);
if (anchor_bits.count(idbit))
continue;
if (cell->input(conn.first))
@ -236,7 +236,7 @@ struct RecoverModuleWorker {
toposort.sort();
for (auto cell_name : toposort.sorted) {
Cell *cell = flat->cell(cell_name);
Cell *cell = flat->cell(flat->design->twines.add(std::string{cell_name.str()}));
int cell_depth = 0;
for (auto conn : cell->connections()) {
if (!cell->input(conn.first))
@ -244,7 +244,7 @@ struct RecoverModuleWorker {
for (auto bit : (*sigmap)(conn.second)) {
if (!bit.wire)
continue;
IdBit idbit(bit.wire->name, bit.offset);
IdBit idbit(bit.wire->name.ref(), bit.offset);
if (!bit2depth.count(idbit))
continue;
cell_depth = std::max(cell_depth, bit2depth.at(idbit));
@ -256,7 +256,7 @@ struct RecoverModuleWorker {
for (auto bit : (*sigmap)(conn.second)) {
if (!bit.wire)
continue;
IdBit idbit(bit.wire->name, bit.offset);
IdBit idbit(bit.wire->name.ref(), bit.offset);
bit2depth[idbit] = std::max(bit2depth[idbit], cell_depth + 1);
}
}
@ -306,7 +306,7 @@ struct RecoverModuleWorker {
for (SigBit in_bit : (*sigmap)(conn.second)) {
if (!in_bit.wire)
continue;
IdBit in_idbit(in_bit.wire->name, in_bit.offset);
IdBit in_idbit(in_bit.wire->name.ref(), in_bit.offset);
to_import.push(in_idbit);
}
}
@ -347,7 +347,7 @@ struct RecoverModuleWorker {
void do_rename(Module *gold, const dict<IdBit, InvBit> &gate2gold, const pool<IdString> &buffer_types)
{
dict<SigBit, std::vector<std::tuple<Cell*, IdString, int>>> bit2port;
dict<SigBit, std::vector<std::tuple<Cell*, TwineRef, int>>> bit2port;
pool<SigBit> unused_bits;
SigMap orig_sigmap(mod);
for (auto wire : mod->wires()) {
@ -380,11 +380,11 @@ struct RecoverModuleWorker {
if (root2buffered.count(gate_bit)) {
int buf_idx = 0;
for (auto buf_bit : root2buffered.at(gate_bit)) {
std::string buf_name_str = stringf("%s_buf_%d", pair.second.bit.name, ++buf_idx);
std::string buf_name_str = stringf("%s_buf_%d", design->twines.str(pair.second.bit.name).c_str(), ++buf_idx);
if (buf_name_str[0] == '\\')
buf_name_str[0] = '$';
rename_map[buf_bit] = std::make_pair(
InvBit(IdBit(IdString(buf_name_str), pair.second.bit.bit), pair.second.inverted), gold_wire);
InvBit(IdBit(design->twines.add(std::string{buf_name_str}), pair.second.bit.bit), pair.second.inverted), gold_wire);
}
}
}
@ -396,11 +396,11 @@ struct RecoverModuleWorker {
bool must_invert_name = rule.second.first.inverted;
while (must_invert_name ||
(mod->wire(new_name.name) && !unused_bits.count(SigBit(mod->wire(new_name.name), new_name.bit)))) {
std::string new_name_str = stringf("%s_%s_%d", rule.second.first.bit.name,
std::string new_name_str = stringf("%s_%s_%d", design->twines.str(rule.second.first.bit.name).c_str(),
rule.second.first.inverted ? "inv" : "dup", ++dup_idx);
if (new_name_str[0] == '\\')
new_name_str[0] = '$';
new_name.name = IdString(new_name_str);
new_name.name = design->twines.add(std::string{new_name_str});
must_invert_name = false;
}
// Create the wire if needed
@ -425,7 +425,7 @@ struct RecoverModuleWorker {
if (bit2port.count(old_bit))
for (auto port_ref : bit2port.at(old_bit)) {
Cell *cell = std::get<0>(port_ref);
IdString port_name = std::get<1>(port_ref);
TwineRef port_name = std::get<1>(port_ref);
int port_bit = std::get<2>(port_ref);
SigSpec port_sig = cell->getPort(port_name);
port_sig.replace(port_bit, new_bit);
@ -461,7 +461,7 @@ struct RecoverNamesWorker {
continue;
bool is_comb = true;
for (auto cell : mod->cells()) {
if (ct_all.cell_evaluable(cell->type)) {
if (ct_all.cell_evaluable(cell->type_impl)) {
is_comb = false;
break;
}

107
passes/sat/sim.cc
View file

@ -250,7 +250,7 @@ struct SimInstance
if (module->get_blackbox_attribute(true))
log_error("Cannot simulate blackbox module %s (instantiated at %s).\n",
design->twines.unescaped_str(module->name), hiername().c_str());
module->design->twines.unescaped_str(module->name.ref()), hiername().c_str());
if (module->has_processes())
log_error("Found processes in simulation hierarchy (in module %s at %s). Run 'proc' first.\n",
@ -275,9 +275,9 @@ struct SimInstance
}
if ((shared->fst) && !(shared->hide_internal && wire->name[0] == '$')) {
fstHandle id = shared->fst->getHandle(scope + "." + design->twines.unescaped_str(wire->name));
fstHandle id = shared->fst->getHandle(scope + "." + module->design->twines.unescaped_str(wire->name.ref()));
if (id==0 && wire->name.isPublic())
log_warning("Unable to find wire %s in input file.\n", (scope + "." + design->twines.unescaped_str(wire->name)));
log_warning("Unable to find wire %s in input file.\n", (scope + "." + module->design->twines.unescaped_str(wire->name.ref())));
fst_handles[wire] = id;
}
@ -413,7 +413,7 @@ struct SimInstance
std::string hiername() const
{
if (instance != nullptr)
return parent->hiername() + "." + design->twines.unescaped_str(instance->name);
return parent->hiername() + "." + module->design->twines.unescaped_str(instance->name.ref());
return module->design->twines.str(module->meta_->name);
}
@ -520,7 +520,7 @@ struct SimInstance
{
auto &state = mem_database[memid];
if (offset >= state.mem->size * state.mem->width)
log_error("Addressing out of bounds bit %d/%d of memory %s\n", offset, state.mem->size * state.mem->width, design->twines.unescaped_str(memid));
log_error("Addressing out of bounds bit %d/%d of memory %s\n", offset, state.mem->size * state.mem->width, log_id(memid));
if (state.data[offset] != data) {
state.data.set(offset, data);
dirty_memories.insert(memid);
@ -553,7 +553,7 @@ struct SimInstance
return;
}
if (yosys_celltypes.cell_evaluable(cell->type))
if (yosys_celltypes.cell_evaluable(cell->type_impl))
{
RTLIL::SigSpec sig_a, sig_b, sig_c, sig_d, sig_s, sig_y;
bool has_a, has_b, has_c, has_d, has_s, has_y;
@ -619,7 +619,7 @@ struct SimInstance
Const data = Const(State::Sx, mem.width << port.wide_log2);
if (port.clk_enable)
log_error("Memory %s.%s has clocked read ports. Run 'memory_nordff' to transform the circuit to remove those.\n", module, design->twines.unescaped_str(mem.memid));
log_error("Memory %s.%s has clocked read ports. Run 'memory_nordff' to transform the circuit to remove those.\n", module, log_id(mem.memid));
if (addr.is_fully_def()) {
int addr_int = addr.as_int();
@ -1027,17 +1027,17 @@ struct SimInstance
child.second->register_signals(id);
}
void write_output_header(std::function<void(TwineRef)> enter_scope, std::function<void()> exit_scope, std::function<void(const char*, int, Wire*, int, bool)> register_signal)
void write_output_header(std::function<void(const std::string&)> enter_scope, std::function<void()> exit_scope, std::function<void(const char*, int, Wire*, int, bool)> register_signal)
{
int exit_scopes = 1;
if (shared->hdlname && instance != nullptr && instance->name.isPublic() && instance->has_attribute(ID::hdlname)) {
auto hdlname = instance->get_hdlname_attribute();
log_assert(!hdlname.empty());
for (auto name : hdlname)
enter_scope("\\" + name);
enter_scope(name);
exit_scopes = hdlname.size();
} else
enter_scope(name());
enter_scope(module->design->twines.unescaped_str(name()));
dict<Wire*,bool> registers;
for (auto cell : module->cells())
@ -1059,7 +1059,7 @@ struct SimInstance
auto signal_name = std::move(hdlname.back());
hdlname.pop_back();
for (auto name : hdlname)
enter_scope("\\" + name);
enter_scope(name);
register_signal(signal_name.c_str(), GetSize(signal.first), signal.first, signal.second.id, registers.count(signal.first)!=0);
for (auto name : hdlname)
exit_scope();
@ -1083,9 +1083,9 @@ struct SimInstance
signal_name = std::move(hdlname.back());
hdlname.pop_back();
for (auto name : hdlname)
enter_scope("\\" + name);
enter_scope(name);
} else {
signal_name = design->twines.unescaped_str(memid);
signal_name = RTLIL::unescape_id(memid);
}
for (auto &trace_index : trace_mem.second) {
@ -1212,7 +1212,7 @@ struct SimInstance
}
}
if (!found)
log_error("Unable to find required '%s' signal in file\n",(scope + "." + design->twines.unescaped_str(sig_y.as_wire()->name)));
log_error("Unable to find required '%s' signal in file\n",(scope + "." + module->design->twines.unescaped_str(sig_y.as_wire()->name.ref())));
}
}
}
@ -1409,10 +1409,11 @@ struct SimWorker : SimShared
{
for (auto portname : ports)
{
Wire *w = top->module->wire(portname);
TwineRef portref = top->module->design->twines.add(std::string{portname.str()});
Wire *w = top->module->wire(portref);
if (w == nullptr)
log_error("Can't find port %s on module %s.\n", design->twines.unescaped_str(portname), top->module);
log_error("Can't find port %s on module %s.\n", top->module->design->twines.unescaped_str(portref), top->module);
top->set_state(w, value);
}
@ -1493,26 +1494,28 @@ struct SimWorker : SimShared
for (auto portname : clock)
{
Wire *w = topmod->wire(portname);
TwineRef portref = topmod->design->twines.add(std::string{portname.str()});
Wire *w = topmod->wire(portref);
if (!w)
log_error("Can't find port %s on module %s.\n", design->twines.unescaped_str(portname), top->module);
log_error("Can't find port %s on module %s.\n", topmod->design->twines.unescaped_str(portref), top->module);
if (!w->port_input)
log_error("Clock port %s on module %s is not input.\n", design->twines.unescaped_str(portname), top->module);
fstHandle id = fst->getHandle(scope + "." + design->twines.unescaped_str(portname));
log_error("Clock port %s on module %s is not input.\n", topmod->design->twines.unescaped_str(portref), top->module);
fstHandle id = fst->getHandle(scope + "." + topmod->design->twines.unescaped_str(portref));
if (id==0)
log_error("Can't find port %s.%s in FST.\n", scope, design->twines.unescaped_str(portname));
log_error("Can't find port %s.%s in FST.\n", scope, topmod->design->twines.unescaped_str(portref));
fst_clock.push_back(id);
}
for (auto portname : clockn)
{
Wire *w = topmod->wire(portname);
TwineRef portref = topmod->design->twines.add(std::string{portname.str()});
Wire *w = topmod->wire(portref);
if (!w)
log_error("Can't find port %s on module %s.\n", design->twines.unescaped_str(portname), top->module);
log_error("Can't find port %s on module %s.\n", topmod->design->twines.unescaped_str(portref), top->module);
if (!w->port_input)
log_error("Clock port %s on module %s is not input.\n", design->twines.unescaped_str(portname), top->module);
fstHandle id = fst->getHandle(scope + "." + design->twines.unescaped_str(portname));
log_error("Clock port %s on module %s is not input.\n", topmod->design->twines.unescaped_str(portref), top->module);
fstHandle id = fst->getHandle(scope + "." + topmod->design->twines.unescaped_str(portref));
if (id==0)
log_error("Can't find port %s.%s in FST.\n", scope, design->twines.unescaped_str(portname));
log_error("Can't find port %s.%s in FST.\n", scope, topmod->design->twines.unescaped_str(portref));
fst_clock.push_back(id);
}
@ -1520,9 +1523,9 @@ struct SimWorker : SimShared
for (auto wire : topmod->wires()) {
if (wire->port_input) {
fstHandle id = fst->getHandle(scope + "." + design->twines.unescaped_str(wire->name));
fstHandle id = fst->getHandle(scope + "." + topmod->design->twines.unescaped_str(wire->name.ref()));
if (id==0)
log_error("Unable to find required '%s' signal in file\n",(scope + "." + design->twines.unescaped_str(wire->name)));
log_error("Unable to find required '%s' signal in file\n",(scope + "." + topmod->design->twines.unescaped_str(wire->name.ref())));
top->fst_inputs[wire] = id;
}
}
@ -1627,10 +1630,10 @@ struct SimWorker : SimShared
if (mf.fail())
log_cmd_error("Not able to read AIGER witness map file.\n");
while (mf >> type >> variable >> index >> symbol) {
RTLIL::IdString escaped_s = RTLIL::escape_id(symbol);
TwineRef escaped_s = topmod->design->twines.add(RTLIL::escape_id(symbol));
Wire *w = topmod->wire(escaped_s);
if (!w) {
escaped_s = RTLIL::escape_id(cell_name(symbol));
escaped_s = topmod->design->twines.add(RTLIL::escape_id(cell_name(symbol)));
Cell *c = topmod->cell(escaped_s);
if (!c)
log_warning("Wire/cell %s not present in module %s\n",symbol,topmod);
@ -2084,13 +2087,13 @@ struct SimWorker : SimShared
json.entry("version", "Yosys sim summary");
json.entry("generator", yosys_maybe_version());
json.entry("steps", step);
json.entry("top", design->twines.unescaped_str(top->module->name));
json.entry("top", top->module->design->twines.unescaped_str(top->module->name.ref()));
json.name("assertions");
json.begin_array();
for (auto &assertion : triggered_assertions) {
json.begin_object();
json.entry("step", assertion.step);
json.entry("type", design->twines.unescaped_str(assertion.cell->type));
json.entry("type", assertion.cell->module->design->twines.unescaped_str(assertion.cell->type_impl));
json.entry("path", assertion.instance->witness_full_path(assertion.cell));
auto src = assertion.cell->get_src_attribute();
if (!src.empty()) {
@ -2153,27 +2156,29 @@ struct SimWorker : SimShared
for (auto portname : clock)
{
Wire *w = topmod->wire(portname);
TwineRef portref = topmod->design->twines.add(std::string{portname.str()});
Wire *w = topmod->wire(portref);
if (!w)
log_error("Can't find port %s on module %s.\n", design->twines.unescaped_str(portname), top->module);
log_error("Can't find port %s on module %s.\n", topmod->design->twines.unescaped_str(portref), top->module);
if (!w->port_input)
log_error("Clock port %s on module %s is not input.\n", design->twines.unescaped_str(portname), top->module);
fstHandle id = fst->getHandle(scope + "." + design->twines.unescaped_str(portname));
log_error("Clock port %s on module %s is not input.\n", topmod->design->twines.unescaped_str(portref), top->module);
fstHandle id = fst->getHandle(scope + "." + topmod->design->twines.unescaped_str(portref));
if (id==0)
log_error("Can't find port %s.%s in FST.\n", scope, design->twines.unescaped_str(portname));
log_error("Can't find port %s.%s in FST.\n", scope, topmod->design->twines.unescaped_str(portref));
fst_clock.push_back(id);
clocks[w] = id;
}
for (auto portname : clockn)
{
Wire *w = topmod->wire(portname);
TwineRef portref = topmod->design->twines.add(std::string{portname.str()});
Wire *w = topmod->wire(portref);
if (!w)
log_error("Can't find port %s on module %s.\n", design->twines.unescaped_str(portname), top->module);
log_error("Can't find port %s on module %s.\n", topmod->design->twines.unescaped_str(portref), top->module);
if (!w->port_input)
log_error("Clock port %s on module %s is not input.\n", design->twines.unescaped_str(portname), top->module);
fstHandle id = fst->getHandle(scope + "." + design->twines.unescaped_str(portname));
log_error("Clock port %s on module %s is not input.\n", topmod->design->twines.unescaped_str(portref), top->module);
fstHandle id = fst->getHandle(scope + "." + topmod->design->twines.unescaped_str(portref));
if (id==0)
log_error("Can't find port %s.%s in FST.\n", scope, design->twines.unescaped_str(portname));
log_error("Can't find port %s.%s in FST.\n", scope, topmod->design->twines.unescaped_str(portref));
fst_clock.push_back(id);
clocks[w] = id;
}
@ -2183,9 +2188,9 @@ struct SimWorker : SimShared
std::map<Wire*,fstHandle> outputs;
for (auto wire : topmod->wires()) {
fstHandle id = fst->getHandle(scope + "." + design->twines.unescaped_str(wire->name));
fstHandle id = fst->getHandle(scope + "." + topmod->design->twines.unescaped_str(wire->name.ref()));
if (id==0 && (wire->port_input || wire->port_output))
log_error("Unable to find required '%s' signal in file\n",(scope + "." + design->twines.unescaped_str(wire->name)));
log_error("Unable to find required '%s' signal in file\n",(scope + "." + topmod->design->twines.unescaped_str(wire->name.ref())));
if (wire->port_input)
if (clocks.find(wire)==clocks.end())
inputs[wire] = id;
@ -2366,7 +2371,7 @@ struct VCDWriter : public OutputWriter
vcdfile << stringf("$timescale %s $end\n", worker->timescale);
worker->top->write_output_header(
[this](IdString name) { vcdfile << stringf("$scope module %s $end\n", design->twines.unescaped_str(name)); },
[this](const std::string& name) { vcdfile << stringf("$scope module %s $end\n", name); },
[this]() { vcdfile << stringf("$upscope $end\n");},
[this,use_signal](const char *name, int size, Wire *w, int id, bool is_reg) {
if (!use_signal.at(id)) return;
@ -2432,7 +2437,7 @@ struct FSTWriter : public OutputWriter
fstWriterSetRepackOnClose(fstfile, 1);
worker->top->write_output_header(
[this](IdString name) { fstWriterSetScope(fstfile, FST_ST_VCD_MODULE, design->twines.unescaped_str(stringf("%s",name)).c_str(), nullptr); },
[this](const std::string& name) { fstWriterSetScope(fstfile, FST_ST_VCD_MODULE, name.c_str(), nullptr); },
[this]() { fstWriterSetUpscope(fstfile); },
[this,use_signal](const char *name, int size, Wire *w, int id, bool is_reg) {
if (!use_signal.at(id)) return;
@ -2492,18 +2497,18 @@ struct AIWWriter : public OutputWriter
if (mf.fail())
log_cmd_error("Not able to read AIGER witness map file.\n");
while (mf >> type >> variable >> index >> symbol) {
RTLIL::IdString escaped_s = RTLIL::escape_id(symbol);
TwineRef escaped_s = worker->top->module->design->twines.add(RTLIL::escape_id(symbol));
Wire *w = worker->top->module->wire(escaped_s);
if (!w)
log_error("Wire %s not present in module design->twines.unescaped_str(%s\n",escaped_s),worker->top->module);
log_error("Wire %s not present in module %s\n", worker->top->module->design->twines.unescaped_str(escaped_s), worker->top->module);
if (index < w->start_offset || index > w->start_offset + w->width)
log_error("Index %d for wire %s is out of range\n", index, log_signal(w));
if (type == "input") {
aiw_inputs[variable] = SigBit(w,index-w->start_offset);
if (worker->clock.count(escaped_s)) {
if (worker->clock.count(RTLIL::escape_id(symbol))) {
clocks[variable] = true;
}
if (worker->clockn.count(escaped_s)) {
if (worker->clockn.count(RTLIL::escape_id(symbol))) {
clocks[variable] = false;
}
max_input = max(max_input,variable);
@ -2518,7 +2523,7 @@ struct AIWWriter : public OutputWriter
}
worker->top->write_output_header(
[](IdString) {},
[](const std::string&) {},
[]() {},
[this](const char */*name*/, int /*size*/, Wire *wire, int id, bool) { if (wire != nullptr) mapping[wire] = id; }
);

6
passes/sat/synthprop.cc
View file

@ -162,7 +162,8 @@ void SynthPropWorker::run()
if (!reset_name.empty()) {
int width = tracing_data[module].names.size();
SigSpec reset = module->wire(TwineSearch(&design->twines).find(reset_name.str()));
TwineSearch search(&design->twines);
SigSpec reset = module->wire(search.find(reset_name.str()));
reset.extend_u0(width, true);
module->addDlatchsr(NEW_TWINE, State::S1, Const(State::S0,width), reset, output, module->wire(port_ref), true, true, reset_pol);
@ -257,7 +258,8 @@ struct SyntProperties : public Pass {
if (top == nullptr)
log_cmd_error("Can't find top module in current design!\n");
auto *reset = top->wire(TwineSearch(&design->twines).find(worker.reset_name.str()));
TwineSearch search(&design->twines);
auto *reset = top->wire(search.find(worker.reset_name.str()));
if (!worker.reset_name.empty() && reset == nullptr)
log_cmd_error("Can't find reset line in current design!\n");

111
passes/techmap/abc.cc
View file

@ -619,7 +619,7 @@ std::string AbcModuleState::remap_name(RTLIL::IdString abc_name, RTLIL::Wire **o
const auto &bit = signal_bits.at(sid);
if (bit.wire != nullptr)
{
std::string s = stringf("$abc$%d$%s", map_autoidx, bit.wire->name.c_str()+1);
std::string s = stringf("$abc$%d$%s", map_autoidx, bit.wire->name.unescaped().c_str());
if (bit.wire->width != 1)
s += stringf("[%d]", bit.offset);
if (isnew)
@ -762,7 +762,7 @@ void AbcModuleState::handle_loops(AbcSigMap &assign_map, RTLIL::Module *module)
std::stringstream sstr;
sstr << "$abcloop$" << (autoidx++);
RTLIL::Wire *wire = module->addWire(sstr.str());
RTLIL::Wire *wire = module->addWire(Twine{sstr.str()});
bool first_line = true;
for (int id2 : edges[id1]) {
@ -982,31 +982,31 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module
clk_polarity = false;
clk_str = clk_str.substr(1);
}
if (module->wire(RTLIL::escape_id(clk_str)) != nullptr)
clk_sig = assign_map(module->wire(RTLIL::escape_id(clk_str)));
if (module->wire(module->design->twines.add(std::string{RTLIL::escape_id(clk_str)})) != nullptr)
clk_sig = assign_map(module->wire(module->design->twines.add(std::string{RTLIL::escape_id(clk_str)})));
if (en_str != "") {
if (en_str[0] == '!') {
en_polarity = false;
en_str = en_str.substr(1);
}
if (module->wire(RTLIL::escape_id(en_str)) != nullptr)
en_sig = assign_map(module->wire(RTLIL::escape_id(en_str)));
if (module->wire(module->design->twines.add(std::string{RTLIL::escape_id(en_str)})) != nullptr)
en_sig = assign_map(module->wire(module->design->twines.add(std::string{RTLIL::escape_id(en_str)})));
}
if (arst_str != "") {
if (arst_str[0] == '!') {
arst_polarity = false;
arst_str = arst_str.substr(1);
}
if (module->wire(RTLIL::escape_id(arst_str)) != nullptr)
arst_sig = assign_map(module->wire(RTLIL::escape_id(arst_str)));
if (module->wire(module->design->twines.add(std::string{RTLIL::escape_id(arst_str)})) != nullptr)
arst_sig = assign_map(module->wire(module->design->twines.add(std::string{RTLIL::escape_id(arst_str)})));
}
if (srst_str != "") {
if (srst_str[0] == '!') {
srst_polarity = false;
srst_str = srst_str.substr(1);
}
if (module->wire(RTLIL::escape_id(srst_str)) != nullptr)
srst_sig = assign_map(module->wire(RTLIL::escape_id(srst_str)));
if (module->wire(module->design->twines.add(std::string{RTLIL::escape_id(srst_str)})) != nullptr)
srst_sig = assign_map(module->wire(module->design->twines.add(std::string{RTLIL::escape_id(srst_str)})));
}
}
@ -1021,7 +1021,7 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module
run_abc.per_run_tempdir_name += proc_program_prefix() + "yosys-abc-XXXXXX";
run_abc.per_run_tempdir_name = make_temp_dir(run_abc.per_run_tempdir_name);
log_header(design, "Extracting gate netlist of module `%s' to `%s/input.blif'..\n",
module->name.c_str(), replace_tempdir(run_abc.per_run_tempdir_name, config.global_tempdir_name, run_abc.per_run_tempdir_name, config.show_tempdir).c_str());
module->name.str().c_str(), replace_tempdir(run_abc.per_run_tempdir_name, config.global_tempdir_name, run_abc.per_run_tempdir_name, config.show_tempdir).c_str());
run_abc.abc_script = stringf("read_blif \"%s/input.blif\"; ", run_abc.per_run_tempdir_name);
@ -1539,18 +1539,19 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
bool builtin_lib = run_abc.config.liberty_files.empty() && run_abc.config.genlib_files.empty();
RTLIL::Design *mapped_design = new RTLIL::Design;
parse_blif(mapped_design, ifs, builtin_lib ? ID(DFF) : ID(_dff_), false, run_abc.config.sop_mode);
parse_blif(mapped_design, ifs, builtin_lib ? TW(DFF) : TW(_dff_), false, run_abc.config.sop_mode);
ifs.close();
log_header(design, "Re-integrating ABC results.\n");
RTLIL::Module *mapped_mod = mapped_design->module(ID(netlist));
auto rn = [&](RTLIL::IdString n) { return module->design->twines.add(std::string{remap_name(n)}); };
RTLIL::Module *mapped_mod = mapped_design->module(TW::netlist);
if (mapped_mod == nullptr)
log_error("ABC output file does not contain a module `netlist'.\n");
bool markgroups = run_abc.config.markgroups;
for (auto w : mapped_mod->wires()) {
RTLIL::Wire *orig_wire = nullptr;
RTLIL::Wire *wire = module->addWire(remap_name(w->name, &orig_wire));
RTLIL::Wire *wire = module->addWire(module->design->twines.add(std::string{remap_name(w->name, &orig_wire)}));
if (orig_wire != nullptr && orig_wire->src_id() != Twine::Null && module->design)
wire->set_src_id(orig_wire->src_id());
if (markgroups) wire->attributes[ID::abcgroup] = map_autoidx;
@ -1568,7 +1569,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
cell_stats[c->type.unescape()]++;
if (c->type.in(ID(ZERO), ID(ONE))) {
RTLIL::SigSig conn;
RTLIL::IdString name_y = remap_name(c->getPort(TW::Y).as_wire()->name);
TwineRef name_y = rn(c->getPort(TW::Y).as_wire()->name);
conn.first = module->wire(name_y);
conn.second = RTLIL::SigSpec(c->type == ID(ZERO) ? 0 : 1, 1);
connect(assign_map, module, conn);
@ -1576,89 +1577,89 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
}
if (c->type == ID(BUF)) {
RTLIL::SigSig conn;
RTLIL::IdString name_y = remap_name(c->getPort(TW::Y).as_wire()->name);
RTLIL::IdString name_a = remap_name(c->getPort(TW::A).as_wire()->name);
TwineRef name_y = rn(c->getPort(TW::Y).as_wire()->name);
TwineRef name_a = rn(c->getPort(TW::A).as_wire()->name);
conn.first = module->wire(name_y);
conn.second = module->wire(name_a);
connect(assign_map, module, conn);
continue;
}
if (c->type == ID(NOT)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), TW($_NOT_));
RTLIL::Cell *cell = module->addCell(rn(c->name), TW($_NOT_));
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::Y}) {
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
for (auto name : {TW::A, TW::Y}) {
TwineRef remapped_name = rn(c->getPort(name).as_wire()->name);
cell->setPort(name, module->wire(remapped_name));
}
design->select(module, cell);
continue;
}
if (c->type.in(ID(AND), ID(OR), ID(XOR), ID(NAND), ID(NOR), ID(XNOR), ID(ANDNOT), ID(ORNOT))) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
RTLIL::Cell *cell = module->addCell(rn(c->name), Twine{stringf("$_%s_", c->type.unescape().c_str())});
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::B, ID::Y}) {
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
for (auto name : {TW::A, TW::B, TW::Y}) {
TwineRef remapped_name = rn(c->getPort(name).as_wire()->name);
cell->setPort(name, module->wire(remapped_name));
}
design->select(module, cell);
continue;
}
if (c->type.in(ID(MUX), ID(NMUX))) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
RTLIL::Cell *cell = module->addCell(rn(c->name), Twine{stringf("$_%s_", c->type.unescape().c_str())});
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::B, ID::S, ID::Y}) {
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
for (auto name : {TW::A, TW::B, TW::S, TW::Y}) {
TwineRef remapped_name = rn(c->getPort(name).as_wire()->name);
cell->setPort(name, module->wire(remapped_name));
}
design->select(module, cell);
continue;
}
if (c->type == ID(MUX4)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), TW($_MUX4_));
RTLIL::Cell *cell = module->addCell(rn(c->name), TW($_MUX4_));
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::B, ID::C, ID::D, ID::S, ID::T, ID::Y}) {
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
for (auto name : {TW::A, TW::B, TW::C, TW::D, TW::S, TW::T, TW::Y}) {
TwineRef remapped_name = rn(c->getPort(name).as_wire()->name);
cell->setPort(name, module->wire(remapped_name));
}
design->select(module, cell);
continue;
}
if (c->type == ID(MUX8)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), TW($_MUX8_));
RTLIL::Cell *cell = module->addCell(rn(c->name), TW($_MUX8_));
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::S, ID::T, ID::U, ID::Y}) {
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
for (auto name : {TW::A, TW::B, TW::C, TW::D, TW::E, TW::F, TW::G, TW::H, TW::S, TW::T, TW::U, TW::Y}) {
TwineRef remapped_name = rn(c->getPort(name).as_wire()->name);
cell->setPort(name, module->wire(remapped_name));
}
design->select(module, cell);
continue;
}
if (c->type == ID(MUX16)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), TW($_MUX16_));
RTLIL::Cell *cell = module->addCell(rn(c->name), TW($_MUX16_));
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::I, ID::J, ID::K,
ID::L, ID::M, ID::N, ID::O, ID::P, ID::S, ID::T, ID::U, ID::V, ID::Y}) {
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
for (auto name : {TW::A, TW::B, TW::C, TW::D, TW::E, TW::F, TW::G, TW::H, TW::I, TW::J, TW::K,
TW::L, TW::M, TW::N, TW::O, TW::P, TW::S, TW::T, TW::U, TW::V, TW::Y}) {
TwineRef remapped_name = rn(c->getPort(name).as_wire()->name);
cell->setPort(name, module->wire(remapped_name));
}
design->select(module, cell);
continue;
}
if (c->type.in(ID(AOI3), ID(OAI3))) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
RTLIL::Cell *cell = module->addCell(rn(c->name), Twine{stringf("$_%s_", c->type.unescape().c_str())});
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::B, ID::C, ID::Y}) {
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
for (auto name : {TW::A, TW::B, TW::C, TW::Y}) {
TwineRef remapped_name = rn(c->getPort(name).as_wire()->name);
cell->setPort(name, module->wire(remapped_name));
}
design->select(module, cell);
continue;
}
if (c->type.in(ID(AOI4), ID(OAI4))) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
RTLIL::Cell *cell = module->addCell(rn(c->name), Twine{stringf("$_%s_", c->type.unescape().c_str())});
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::B, ID::C, ID::D, ID::Y}) {
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
for (auto name : {TW::A, TW::B, TW::C, TW::D, TW::Y}) {
TwineRef remapped_name = rn(c->getPort(name).as_wire()->name);
cell->setPort(name, module->wire(remapped_name));
}
design->select(module, cell);
@ -1697,8 +1698,8 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
ff.sig_srst = srst_sig;
ff.val_srst = init;
}
ff.sig_d = module->wire(remap_name(c->getPort(TW::D).as_wire()->name));
ff.sig_q = module->wire(remap_name(c->getPort(TW::Q).as_wire()->name));
ff.sig_d = module->wire(rn(c->getPort(TW::D).as_wire()->name));
ff.sig_q = module->wire(rn(c->getPort(TW::Q).as_wire()->name));
RTLIL::Cell *cell = ff.emit();
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
design->select(module, cell);
@ -1710,7 +1711,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
if (c->type.in(ID(_const0_), ID(_const1_))) {
RTLIL::SigSig conn;
conn.first = module->wire(remap_name(c->connections().begin()->second.as_wire()->name));
conn.first = module->wire(rn(c->connections().begin()->second.as_wire()->name));
conn.second = RTLIL::SigSpec(c->type == ID(_const0_) ? 0 : 1, 1);
connect(assign_map, module, conn);
continue;
@ -1746,8 +1747,8 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
ff.sig_srst = srst_sig;
ff.val_srst = init;
}
ff.sig_d = module->wire(remap_name(c->getPort(TW::D).as_wire()->name));
ff.sig_q = module->wire(remap_name(c->getPort(TW::Q).as_wire()->name));
ff.sig_d = module->wire(rn(c->getPort(TW::D).as_wire()->name));
ff.sig_q = module->wire(rn(c->getPort(TW::Q).as_wire()->name));
RTLIL::Cell *cell = ff.emit();
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
design->select(module, cell);
@ -1755,13 +1756,13 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
}
if (c->type == TW($lut) && GetSize(c->getPort(TW::A)) == 1 && c->getParam(ID::LUT).as_int() == 2) {
SigSpec my_a = module->wire(remap_name(c->getPort(TW::A).as_wire()->name));
SigSpec my_y = module->wire(remap_name(c->getPort(TW::Y).as_wire()->name));
SigSpec my_a = module->wire(rn(c->getPort(TW::A).as_wire()->name));
SigSpec my_y = module->wire(rn(c->getPort(TW::Y).as_wire()->name));
connect(assign_map, module, RTLIL::SigSig(my_a, my_y));
continue;
}
RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type);
RTLIL::Cell *cell = module->addCell(rn(c->name), c->type_impl);
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
cell->parameters = c->parameters;
for (auto &conn : c->connections()) {
@ -1770,7 +1771,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
if (c.width == 0)
continue;
log_assert(c.width == 1);
newsig.append(module->wire(remap_name(c.wire->name)));
newsig.append(module->wire(rn(c.wire->name)));
}
cell->setPort(conn.first, newsig);
}
@ -1779,9 +1780,9 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
for (auto conn : mapped_mod->connections()) {
if (!conn.first.is_fully_const())
conn.first = module->wire(remap_name(conn.first.as_wire()->name));
conn.first = module->wire(rn(conn.first.as_wire()->name));
if (!conn.second.is_fully_const())
conn.second = module->wire(remap_name(conn.second.as_wire()->name));
conn.second = module->wire(rn(conn.second.as_wire()->name));
connect(assign_map, module, conn);
}
@ -1796,10 +1797,10 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
RTLIL::SigSig conn;
if (si.type != G(NONE)) {
conn.first = signal_bits[si.id];
conn.second = module->wire(remap_name(buffer));
conn.second = module->wire(rn(buffer));
out_wires++;
} else {
conn.first = module->wire(remap_name(buffer));
conn.first = module->wire(rn(buffer));
conn.second = signal_bits[si.id];
in_wires++;
}

7
passes/techmap/abc9.cc
View file

@ -318,12 +318,13 @@ struct Abc9Pass : public ScriptPass
}
else {
// Rename all submod-s to _TECHMAP_REPLACE_ to inherit name + attrs
TwineSearch search(&active_design->twines);
for (auto module : active_design->selected_modules()) {
active_design->selected_active_module = module->name.str();
if (module->cell(stringf("%s_$abc9_flop", module->name)))
active_design->selected_active_module = module->name.ref();
if (module->cell(search.find(stringf("%s_$abc9_flop", module->name))))
run(stringf("rename %s_$abc9_flop _TECHMAP_REPLACE_", module->name));
}
active_design->selected_active_module.clear();
active_design->selected_active_module = Twine::Null;
}
run("abc9_ops -prep_dff_unmap", " (only if -dff)");
run("design -copy-to $abc9 =*_$abc9_flop", " (only if -dff)"); // copy submod out

276
passes/techmap/abc9_ops.cc
View file

@ -37,7 +37,7 @@ inline std::string remap_name(RTLIL::IdString abc9_name)
void check(RTLIL::Design *design, bool dff_mode)
{
dict<IdString,IdString> box_lookup;
dict<IdString,TwineRef> box_lookup;
for (auto m : design->modules()) {
auto flop = m->get_bool_attribute(ID::abc9_flop);
auto it = m->attributes.find(ID::abc9_box_id);
@ -45,7 +45,7 @@ void check(RTLIL::Design *design, bool dff_mode)
if (it == m->attributes.end())
continue;
auto id = it->second.as_int();
auto r = box_lookup.insert(std::make_pair(stringf("$__boxid%d", id), RTLIL::IdString(m->name)));
auto r = box_lookup.insert(std::make_pair(stringf("$__boxid%d", id), m->name.ref()));
if (!r.second)
log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
m, id, design->twines.unescaped_str(r.first->second));
@ -53,27 +53,27 @@ void check(RTLIL::Design *design, bool dff_mode)
// Make carry in the last PI, and carry out the last PO
// since ABC requires it this way
IdString carry_in, carry_out;
TwineRef carry_in = Twine::Null, carry_out = Twine::Null;
for (const auto &port_name : m->ports) {
auto w = m->wire(port_name);
log_assert(w);
if (w->get_bool_attribute(ID::abc9_carry)) {
if (w->port_input) {
if (carry_in != IdString())
if (carry_in != Twine::Null)
log_error("Module '%s' contains more than one (* abc9_carry *) input port.\n", m);
carry_in = port_name;
}
if (w->port_output) {
if (carry_out != IdString())
if (carry_out != Twine::Null)
log_error("Module '%s' contains more than one (* abc9_carry *) output port.\n", m);
carry_out = port_name;
}
}
}
if (carry_in != IdString() && carry_out == IdString())
if (carry_in != Twine::Null && carry_out == Twine::Null)
log_error("Module '%s' contains an (* abc9_carry *) input port but no output port.\n", m);
if (carry_in == IdString() && carry_out != IdString())
if (carry_in == Twine::Null && carry_out != Twine::Null)
log_error("Module '%s' contains an (* abc9_carry *) output port but no input port.\n", m);
if (flop) {
@ -88,7 +88,7 @@ void check(RTLIL::Design *design, bool dff_mode)
}
if (dff_mode) {
static pool<IdString> unsupported{
static pool<TwineRef> unsupported{
TW($adff), TW($dlatch), TW($dlatchsr), TW($sr),
TW($_DFF_NN0_), TW($_DFF_NN1_), TW($_DFF_NP0_), TW($_DFF_NP1_),
TW($_DFF_PN0_), TW($_DFF_PN1_), TW($_DFF_PP0_), TW($_DFF_PP1_),
@ -102,10 +102,10 @@ void check(RTLIL::Design *design, bool dff_mode)
auto inst_module = design->module(cell->type_impl);
if (!inst_module)
continue;
IdString derived_type;
TwineRef derived_type;
Module *derived_module;
if (cell->parameters.empty()) {
derived_type = cell->type;
derived_type = cell->type_impl;
derived_module = inst_module;
}
else {
@ -136,13 +136,13 @@ void check(RTLIL::Design *design, bool dff_mode)
log_assert(GetSize(Q.wire) == 1);
if (!Q.wire->port_output)
log_error("Whitebox '%s' with (* abc9_flop *) contains a %s cell where its 'Q' port does not drive a module output.\n", derived_module, design->twines.unescaped_str(derived_cell->type));
log_error("Whitebox '%s' with (* abc9_flop *) contains a %s cell where its 'Q' port does not drive a module output.\n", derived_module, derived_cell->type.unescape());
Const init = Q.wire->attributes.at(ID::init, State::Sx);
log_assert(GetSize(init) == 1);
}
else if (unsupported.count(derived_cell->type))
log_error("Whitebox '%s' with (* abc9_flop *) contains a %s cell, which is not supported for sequential synthesis.\n", derived_module, design->twines.unescaped_str(derived_cell->type));
else if (unsupported.count(derived_cell->type.ref()))
log_error("Whitebox '%s' with (* abc9_flop *) contains a %s cell, which is not supported for sequential synthesis.\n", derived_module, derived_cell->type.unescape());
}
}
}
@ -154,19 +154,20 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
if (r.second)
r.first->second = new Design;
Design *unmap_design = r.first->second;
auto to_unmap = [&](TwineRef t) { return unmap_design->twines.add(std::string{design->twines.str(t)}); };
// Keep track of derived versions of modules that we haven't used, to prevent these being used for unwanted techmaps later on.
pool<IdString> unused_derived;
pool<TwineRef> unused_derived;
for (auto module : design->selected_modules())
for (auto cell : module->cells()) {
auto inst_module = design->module(cell->type_impl);
if (!inst_module)
continue;
IdString derived_type;
TwineRef derived_type;
Module *derived_module;
if (cell->parameters.empty()) {
derived_type = cell->type;
derived_type = cell->type_impl;
derived_module = inst_module;
}
else {
@ -190,11 +191,11 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
}
}
if (!derived_module->get_bool_attribute(ID::abc9_box) && !derived_module->get_bool_attribute(ID::abc9_bypass) && !has_timing) {
if (unmap_design->module(derived_type)) {
if (unmap_design->module(to_unmap(derived_type))) {
// If derived_type is present in unmap_design, it means that it was processed previously, but found to be incompatible -- e.g. if
// it contained a non-zero initial state. In this case, continue to replace the cell type/parameters so that it has the same properties
// as a compatible type, yet will be safely unmapped later
cell->type_impl = cell->module->design->twines.add(Twine{derived_type.str()});
cell->type_impl = derived_type;
cell->parameters.clear();
unused_derived.erase(derived_type);
}
@ -202,7 +203,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
}
}
if (!unmap_design->module(derived_type)) {
if (!unmap_design->module(to_unmap(derived_type))) {
if (derived_module->has_processes())
Pass::call_on_module(design, derived_module, "proc -noopt");
@ -216,7 +217,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
// Block sequential synthesis on cells with (* init *) != 1'b0
// because ABC9 doesn't support them
if (init != State::S0) {
log_warning("Whitebox '%s' with (* abc9_flop *) contains a %s cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox.\n", derived_module, design->twines.unescaped_str(derived_cell->type));
log_warning("Whitebox '%s' with (* abc9_flop *) contains a %s cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox.\n", derived_module, derived_cell->type.unescape());
derived_module->set_bool_attribute(ID::abc9_flop, false);
}
break;
@ -231,11 +232,11 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
}
}
if (derived_type != cell->type) {
auto unmap_module = unmap_design->addModule(derived_type);
auto replace_cell = unmap_module->addCell(ID::_TECHMAP_REPLACE_, cell->type);
if (derived_type != cell->type_impl) {
auto unmap_module = unmap_design->addModule(to_unmap(derived_type));
auto replace_cell = unmap_module->addCell(TW::_TECHMAP_REPLACE_, Twine{cell->type.str()});
for (auto port : derived_module->ports) {
auto w = unmap_module->addWire(port, derived_module->wire(port));
auto w = unmap_module->addWire(to_unmap(port), derived_module->wire(port));
// Do not propagate (* init *) values into the box,
// in fact, remove it from outside too
if (w->port_output)
@ -245,16 +246,18 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
// the techmapped cell
w->attributes[ID::techmap_autopurge] = 1;
replace_cell->setPort(port, w);
replace_cell->setPort(to_unmap(port), w);
}
unmap_module->ports = derived_module->ports;
unmap_module->ports.clear();
for (auto port : derived_module->ports)
unmap_module->ports.push_back(to_unmap(port));
unmap_module->check();
replace_cell->parameters = cell->parameters;
}
}
cell->type_impl = cell->module->design->twines.add(Twine{derived_type.str()});
cell->type_impl = derived_type;
cell->parameters.clear();
unused_derived.erase(derived_type);
}
@ -274,11 +277,13 @@ void prep_bypass(RTLIL::Design *design)
if (r.second)
r.first->second = new Design;
Design *unmap_design = r.first->second;
auto to_map = [&](TwineRef t) { return map_design->twines.add(std::string{design->twines.str(t)}); };
auto to_unmap = [&](TwineRef t) { return unmap_design->twines.add(std::string{design->twines.str(t)}); };
pool<IdString> processed;
pool<TwineRef> processed;
for (auto module : design->selected_modules())
for (auto cell : module->cells()) {
if (!processed.insert(cell->type).second)
if (!processed.insert(cell->type.ref()).second)
continue;
auto inst_module = design->module(cell->type_impl);
if (!inst_module)
@ -320,26 +325,28 @@ void prep_bypass(RTLIL::Design *design)
// Copy inst_module into map_design, with the same interface
// and duplicate $abc9$* wires for its output ports
auto map_module = map_design->addModule(cell->type.ref());
auto map_module = map_design->addModule(to_map(cell->type.ref()));
for (auto port_name : inst_module->ports) {
auto w = map_module->addWire(port_name, inst_module->wire(port_name));
auto w = map_module->addWire(to_map(port_name), inst_module->wire(port_name));
if (w->port_output)
w->attributes.erase(ID::init);
}
map_module->ports = inst_module->ports;
map_module->ports.clear();
for (auto port_name : inst_module->ports)
map_module->ports.push_back(to_map(port_name));
map_module->check();
map_module->set_bool_attribute(ID::whitebox);
// Create the bypass module in the user design, which has the same
// interface as the derived module but with additional input
// ports driven by the outputs of the replaced cell
auto bypass_module = design->addModule(cell->type.str() + "_$abc9_byp");
auto bypass_module = design->addModule(design->twines.add(cell->type.str() + "_$abc9_byp"));
for (auto port_name : inst_module->ports) {
auto port = inst_module->wire(port_name);
if (!port->port_output)
continue;
auto dst = bypass_module->addWire(port_name, port);
auto src = bypass_module->addWire("$abc9byp$" + port_name.str(), GetSize(port));
auto src = bypass_module->addWire(Twine{"$abc9byp$" + design->twines.str(port_name)}, GetSize(port));
src->port_input = true;
// For these new input ports driven by the replaced
// cell, then create a new simple-path specify entry:
@ -396,9 +403,9 @@ void prep_bypass(RTLIL::Design *design)
SigSpec new_sig;
for (auto c : sig.chunks()) {
if (c.wire) {
auto port = bypass_module->wire(c.wire->name);
auto port = bypass_module->wire(c.wire->name.ref());
if (!port)
port = bypass_module->addWire(c.wire->name, c.wire);
port = bypass_module->addWire(c.wire->name.ref(), c.wire);
c.wire = port;
}
new_sig.append(std::move(c));
@ -414,21 +421,21 @@ void prep_bypass(RTLIL::Design *design)
// and a bypass cell that has the same inputs/outputs as the
// original cell, but with additional inputs taken from the
// replaced cell
auto replace_cell = map_module->addCell(ID::_TECHMAP_REPLACE_, cell->type);
auto bypass_cell = map_module->addCell(NEW_TWINE, cell->type.str() + "_$abc9_byp");
auto replace_cell = map_module->addCell(TW::_TECHMAP_REPLACE_, Twine{cell->type.str()});
auto bypass_cell = map_module->addCell(NEW_TWINE, Twine{cell->type.str() + "_$abc9_byp"});
for (const auto &conn : cell->connections()) {
auto port = map_module->wire(conn.first);
auto port = map_module->wire(to_map(conn.first));
if (cell->input(conn.first)) {
replace_cell->setPort(conn.first, port);
replace_cell->setPort(to_map(conn.first), port);
if (bypass_module->wire(conn.first))
bypass_cell->setPort(conn.first, port);
bypass_cell->setPort(to_map(conn.first), port);
}
if (cell->output(conn.first)) {
bypass_cell->setPort(conn.first, port);
auto n = "$abc9byp$" + conn.first.str();
auto w = map_module->addWire(n, GetSize(conn.second));
replace_cell->setPort(conn.first, w);
bypass_cell->setPort(n, w);
bypass_cell->setPort(to_map(conn.first), port);
auto n = "$abc9byp$" + design->twines.str(conn.first);
auto w = map_module->addWire(Twine{n}, GetSize(conn.second));
replace_cell->setPort(to_map(conn.first), w);
bypass_cell->setPort(map_design->twines.add(Twine{n}), w);
}
}
@ -436,12 +443,12 @@ void prep_bypass(RTLIL::Design *design)
// Lastly, create a new module in the unmap_design that shorts
// out the bypass cell back to leave the replace cell behind
// driving the outputs
auto unmap_module = unmap_design->addModule(cell->type.str() + "_$abc9_byp");
auto unmap_module = unmap_design->addModule(unmap_design->twines.add(cell->type.str() + "_$abc9_byp"));
for (auto port_name : inst_module->ports) {
auto w = unmap_module->addWire(port_name, inst_module->wire(port_name));
auto w = unmap_module->addWire(to_unmap(port_name), inst_module->wire(port_name));
if (w->port_output) {
w->attributes.erase(ID::init);
auto w2 = unmap_module->addWire("$abc9byp$" + port_name.str(), GetSize(w));
auto w2 = unmap_module->addWire(Twine{"$abc9byp$" + design->twines.str(port_name)}, GetSize(w));
w2->port_input = true;
unmap_module->connect(w, w2);
}
@ -454,7 +461,7 @@ void prep_bypass(RTLIL::Design *design)
void prep_dff(RTLIL::Design *design)
{
auto r = design->selection_vars.insert(std::make_pair(TW($abc9_flops), RTLIL::Selection::EmptySelection(design)));
auto r = design->selection_vars.insert(std::make_pair(ID($abc9_flops), RTLIL::Selection::EmptySelection(design)));
auto &modules_sel = r.first->second;
for (auto module : design->selected_modules())
@ -523,15 +530,16 @@ void prep_dff_submod(RTLIL::Design *design)
void prep_dff_unmap(RTLIL::Design *design)
{
Design *unmap_design = saved_designs.at("$abc9_unmap");
auto to_unmap = [&](TwineRef t) { return unmap_design->twines.add(std::string{design->twines.str(t)}); };
for (auto module : design->modules()) {
if (!module->get_bool_attribute(ID::abc9_flop) || module->get_bool_attribute(ID::abc9_box))
continue;
// Make sure the box module has all the same ports present on flop cell
auto replace_cell = module->cell(ID::_TECHMAP_REPLACE_);
auto replace_cell = module->cell(TW::_TECHMAP_REPLACE_);
log_assert(replace_cell);
auto box_module = design->module(module->name.str() + "_$abc9_flop");
auto box_module = design->module(design->twines.add(module->name.str() + "_$abc9_flop"));
log_assert(box_module);
for (auto port_name : module->ports) {
auto port = module->wire(port_name);
@ -547,14 +555,16 @@ void prep_dff_unmap(RTLIL::Design *design)
}
box_module->fixup_ports();
auto unmap_module = unmap_design->addModule(box_module->name);
replace_cell = unmap_module->addCell(ID::_TECHMAP_REPLACE_, module->name);
auto unmap_module = unmap_design->addModule(to_unmap(box_module->name.ref()));
replace_cell = unmap_module->addCell(TW::_TECHMAP_REPLACE_, Twine{module->name.str()});
for (auto port_name : box_module->ports) {
auto w = unmap_module->addWire(port_name, box_module->wire(port_name));
auto w = unmap_module->addWire(to_unmap(port_name), box_module->wire(port_name));
if (module->wire(port_name))
replace_cell->setPort(port_name, w);
replace_cell->setPort(to_unmap(port_name), w);
}
unmap_module->ports = box_module->ports;
unmap_module->ports.clear();
for (auto port_name : box_module->ports)
unmap_module->ports.push_back(to_unmap(port_name));
unmap_module->check();
}
}
@ -647,7 +657,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
// as delays will be captured in the flop box
}
if (!timing.count(cell->type))
if (!timing.count(cell->type.ref()))
timing.setup_module(inst_module);
cells.emplace_back(cell);
@ -656,7 +666,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
// Insert $__ABC9_DELAY cells on all cells that instantiate blackboxes
// (or bypassed white-boxes with required times)
dict<int, IdString> box_cache;
dict<int, TwineRef> box_cache;
Module *delay_module = design->module(TW($__ABC9_DELAY));
log_assert(delay_module);
for (auto cell : cells) {
@ -664,11 +674,11 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
auto inst_module = design->module(cell->type_impl);
log_assert(inst_module);
for (auto &i : timing.at(cell->type).required) {
for (auto &i : timing.at(cell->type.ref()).required) {
auto port_wire = inst_module->wire(i.first.name);
if (!port_wire)
log_error("Port %s in cell %s (type %s) from module %s does not actually exist",
i.first.name.unescape(), cell, cell->type.unescaped(), module);
design->twines.unescaped_str(i.first.name), cell, cell->type.unescaped(), module);
log_assert(port_wire->port_input);
auto d = i.second.first;
@ -693,7 +703,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
auto r = box_cache.insert(d);
if (r.second) {
r.first->second = delay_module->derive(design, {{ID::DELAY, d}});
log_assert(r.first->second.begins_with("$paramod$__ABC9_DELAY\\DELAY="));
log_assert(design->twines.str(r.first->second).starts_with("$paramod$__ABC9_DELAY\\DELAY="));
}
auto box = module->addCell(NEW_TWINE, r.first->second);
box->setPort(TW::I, rhs[offset]);
@ -708,10 +718,11 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
{
auto design = module->design;
log_assert(design);
auto refof = [&](RTLIL::IdString n) { return design->twines.add(std::string{n.str()}); };
SigMap sigmap(module);
dict<IdString, std::vector<IdString>> box_ports;
dict<TwineRef, std::vector<TwineRef>> box_ports;
for (auto cell : module->cells()) {
if (cell->type.in(TW($_DFF_N_), TW($_DFF_P_)))
@ -725,11 +736,11 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
continue;
if (inst_module && inst_module->get_bool_attribute(ID::abc9_box)) {
auto r = box_ports.insert(cell->type);
auto r = box_ports.insert(cell->type.ref());
if (r.second) {
// Make carry in the last PI, and carry out the last PO
// since ABC requires it this way
IdString carry_in, carry_out;
TwineRef carry_in = Twine::Null, carry_out = Twine::Null;
for (const auto &port_name : inst_module->ports) {
auto w = inst_module->wire(port_name);
log_assert(w);
@ -743,7 +754,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
else
r.first->second.push_back(port_name);
}
if (carry_in != IdString()) {
if (carry_in != Twine::Null) {
r.first->second.push_back(carry_in);
r.first->second.push_back(carry_out);
}
@ -811,7 +822,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
// Loop reports can overlap; cut each cell at most once.
if (!broken_cells.insert(cell_name).second)
continue;
auto cell = module->cell(cell_name);
auto cell = module->cell(refof(cell_name));
log_assert(cell);
auto inst_module = design->module(cell->type_impl);
if (inst_module && inst_module->get_bool_attribute(ID::abc9_box))
@ -845,7 +856,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
for (auto &it : toposort.value().loops) {
log(" loop %d\n", i++);
for (auto cell_name : it) {
auto cell = module->cell(cell_name);
auto cell = module->cell(refof(cell_name));
log_assert(cell);
log("\t%s (%s @ %s)\n", cell, cell->type.unescaped(), cell->get_src_attribute());
}
@ -859,7 +870,8 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
r.first->second = new Design;
RTLIL::Design *holes_design = r.first->second;
log_assert(holes_design);
RTLIL::Module *holes_module = holes_design->addModule(module->name);
auto to_holes = [&](TwineRef t) { return holes_design->twines.add(std::string{design->twines.str(t)}); };
RTLIL::Module *holes_module = holes_design->addModule(to_holes(module->name.ref()));
log_assert(holes_module);
dict<IdString, Cell*> cell_cache;
@ -867,7 +879,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
int port_id = 1, box_count = 0;
for (auto cell_name : toposort.value().sorted) {
RTLIL::Cell *cell = module->cell(cell_name);
RTLIL::Cell *cell = module->cell(refof(cell_name));
log_assert(cell);
RTLIL::Module* box_module = design->module(cell->type_impl);
@ -881,7 +893,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
// be instantiating the derived module which will have had any parameters constant-propagated.
// This task is expected to be performed by `abc9_ops -prep_hier`, but it looks like it failed to do so for this design.
// Please file a bug report!
log_error("Not expecting parameters on cell '%s' instantiating module '%s' marked (* abc9_box *)\n", design->twines.unescaped_str(cell_name), cell->type.unescaped());
log_error("Not expecting parameters on cell '%s' instantiating module '%s' marked (* abc9_box *)\n", design->twines.unescaped_str(refof(cell_name)), cell->type.unescaped());
}
log_assert(box_module->get_blackbox_attribute());
@ -891,49 +903,49 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
auto &holes_cell = r.first->second;
if (r.second) {
if (box_module->get_bool_attribute(ID::whitebox)) {
holes_cell = holes_module->addCell(NEW_TWINE, cell->type);
holes_cell = holes_module->addCell(NEW_TWINE, Twine{cell->type.str()});
if (box_module->has_processes())
Pass::call_on_module(design, box_module, "proc -noopt");
int box_inputs = 0;
for (auto port_name : box_ports.at(cell->type)) {
for (auto port_name : box_ports.at(cell->type.ref())) {
RTLIL::Wire *w = box_module->wire(port_name);
log_assert(w);
log_assert(!w->port_input || !w->port_output);
auto &conn = holes_cell->connections_[port_name];
auto &conn = holes_cell->connections_[to_holes(port_name)];
if (w->port_input) {
for (int i = 0; i < GetSize(w); i++) {
box_inputs++;
RTLIL::Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
RTLIL::Wire *holes_wire = holes_module->wire(holes_design->twines.add(stringf("\\i%d", box_inputs)));
if (!holes_wire) {
holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
holes_wire = holes_module->addWire(holes_design->twines.add(stringf("\\i%d", box_inputs)));
holes_wire->port_input = true;
holes_wire->port_id = port_id++;
holes_module->ports.push_back(holes_wire->name);
holes_module->ports.push_back(holes_wire->name.ref());
}
conn.append(holes_wire);
}
}
else if (w->port_output)
conn = holes_module->addWire(stringf("%s.%s", cell->type, design->twines.unescaped_str(port_name)), GetSize(w));
conn = holes_module->addWire(Twine{stringf("%s.%s", cell->type, design->twines.unescaped_str(port_name))}, GetSize(w));
}
}
else // box_module is a blackbox
log_assert(holes_cell == nullptr);
}
for (auto port_name : box_ports.at(cell->type)) {
for (auto port_name : box_ports.at(cell->type.ref())) {
RTLIL::Wire *w = box_module->wire(port_name);
log_assert(w);
if (!w->port_output)
continue;
Wire *holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name, design->twines.unescaped_str(port_name)), GetSize(w));
Wire *holes_wire = holes_module->addWire(Twine{stringf("$abc%s.%s", cell->name, design->twines.unescaped_str(port_name))}, GetSize(w));
holes_wire->port_output = true;
holes_wire->port_id = port_id++;
holes_module->ports.push_back(holes_wire->name);
holes_module->ports.push_back(holes_wire->name.ref());
if (holes_cell) // whitebox
holes_module->connect(holes_wire, holes_cell->getPort(port_name));
holes_module->connect(holes_wire, holes_cell->getPort(to_holes(port_name)));
else // blackbox
holes_module->connect(holes_wire, Const(State::S0, GetSize(w)));
}
@ -945,7 +957,7 @@ void prep_lut(RTLIL::Design *design, int maxlut)
TimingInfo timing;
struct t_lut {
IdString name;
TwineRef name;
int area;
std::vector<int> delays;
};
@ -976,7 +988,7 @@ void prep_lut(RTLIL::Design *design, int maxlut)
std::sort(delays.begin(), delays.end());
int K = GetSize(delays);
auto entry = t_lut{module->name, it->second.as_int(), std::move(delays)};
auto entry = t_lut{module->name.ref(), it->second.as_int(), std::move(delays)};
auto r = table.emplace(K, entry);
if (!r.second) {
if (r.first->second.area != entry.area)
@ -1023,7 +1035,7 @@ void prep_box(RTLIL::Design *design)
int abc9_box_id = 1;
std::stringstream ss;
dict<IdString,std::vector<IdString>> box_ports;
dict<TwineRef,std::vector<TwineRef>> box_ports;
for (auto module : design->modules()) {
auto it = module->attributes.find(ID::abc9_box);
if (it == module->attributes.end())
@ -1060,7 +1072,7 @@ void prep_box(RTLIL::Design *design)
first = false;
else
ss << " ";
ss << design->twines.unescaped_str(wire->name);
ss << design->twines.unescaped_str(wire->name.ref());
}
ss << std::endl;
@ -1087,9 +1099,9 @@ void prep_box(RTLIL::Design *design)
#ifndef NDEBUG
if (ys_debug(1)) {
static std::set<std::pair<IdString,IdString>> seen;
static std::set<std::pair<IdString,TwineRef>> seen;
if (seen.emplace(module->name, port_name).second) log("%s.%s abc9_required = %d\n", module,
port_name.unescape(), it->second.first);
design->twines.unescaped_str(port_name), it->second.first);
}
#endif
}
@ -1098,11 +1110,11 @@ void prep_box(RTLIL::Design *design)
ss << std::endl;
}
else {
auto r2 = box_ports.insert(module->name);
auto r2 = box_ports.insert(module->name.ref());
if (r2.second) {
// Make carry in the last PI, and carry out the last PO
// since ABC requires it this way
IdString carry_in, carry_out;
TwineRef carry_in = Twine::Null, carry_out = Twine::Null;
for (const auto &port_name : module->ports) {
auto w = module->wire(port_name);
log_assert(w);
@ -1117,7 +1129,7 @@ void prep_box(RTLIL::Design *design)
r2.first->second.push_back(port_name);
}
if (carry_in != IdString()) {
if (carry_in != Twine::Null) {
r2.first->second.push_back(carry_in);
r2.first->second.push_back(carry_out);
}
@ -1147,9 +1159,9 @@ void prep_box(RTLIL::Design *design)
else
ss << " ";
if (GetSize(i.wire) == 1)
ss << design->twines.unescaped_str(i.wire->name);
ss << design->twines.unescaped_str(i.wire->name.ref());
else
ss << design->twines.unescaped_str(i.wire->name) << "[" << i.offset << "]";
ss << design->twines.unescaped_str(i.wire->name.ref()) << "[" << i.offset << "]";
}
ss << std::endl;
@ -1173,9 +1185,9 @@ void prep_box(RTLIL::Design *design)
}
ss << " # ";
if (GetSize(o.wire) == 1)
ss << design->twines.unescaped_str(o.wire->name);
ss << design->twines.unescaped_str(o.wire->name.ref());
else
ss << design->twines.unescaped_str(o.wire->name) << "[" << o.offset << "]";
ss << design->twines.unescaped_str(o.wire->name.ref()) << "[" << o.offset << "]";
ss << std::endl;
}
ss << std::endl;
@ -1202,31 +1214,33 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
log_assert(design);
map_autoidx = autoidx++;
auto rn = [&](RTLIL::IdString n) { return design->twines.add(std::string{remap_name(n)}); };
auto refof = [&](RTLIL::IdString n) { return design->twines.add(std::string{n.str()}); };
RTLIL::Module *mapped_mod = design->module(stringf("%s$abc9", module->name));
RTLIL::Module *mapped_mod = design->module(design->twines.add(stringf("%s$abc9", module->name)));
if (mapped_mod == NULL)
log_error("ABC output file does not contain a module `%s$abc'.\n", module);
for (auto w : mapped_mod->wires()) {
auto nw = module->addWire(remap_name(w->name), GetSize(w));
auto nw = module->addWire(rn(w->name), GetSize(w));
nw->start_offset = w->start_offset;
// Remove all (* init *) since they only exist on $_DFF_[NP]_
w->attributes.erase(ID::init);
}
dict<IdString,std::vector<IdString>> box_ports;
dict<TwineRef,std::vector<TwineRef>> box_ports;
for (auto m : design->modules()) {
if (!m->attributes.count(ID::abc9_box_id))
continue;
auto r = box_ports.insert(m->name);
auto r = box_ports.insert(m->name.ref());
if (!r.second)
continue;
// Make carry in the last PI, and carry out the last PO
// since ABC requires it this way
IdString carry_in, carry_out;
TwineRef carry_in = Twine::Null, carry_out = Twine::Null;
for (const auto &port_name : m->ports) {
auto w = m->wire(port_name);
log_assert(w);
@ -1241,7 +1255,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
r.first->second.push_back(port_name);
}
if (carry_in != IdString()) {
if (carry_in != Twine::Null) {
r.first->second.push_back(carry_in);
r.first->second.push_back(carry_out);
}
@ -1298,8 +1312,8 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
SigBit D = mapped_cell->getPort(TW::D);
SigBit Q = mapped_cell->getPort(TW::Q);
if (D.wire)
D.wire = module->wire(remap_name(D.wire->name));
Q.wire = module->wire(remap_name(Q.wire->name));
D.wire = module->wire(rn(D.wire->name));
Q.wire = module->wire(rn(Q.wire->name));
module->connect(Q, D);
continue;
}
@ -1317,7 +1331,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
if (!a_bit.wire) {
mapped_cell->setPort(TW::Y, module->addWire(NEW_TWINE));
RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name));
RTLIL::Wire *wire = module->wire(rn(y_bit.wire->name));
log_assert(wire);
module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1);
}
@ -1334,18 +1348,18 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
driver_name = stringf("$lut%s", a_bit.wire->name);
else
driver_name = stringf("$lut%s[%d]", a_bit.wire->name, a_bit.offset);
driver_lut = mapped_mod->cell(driver_name);
driver_lut = mapped_mod->cell(refof(driver_name));
}
if (!driver_lut) {
// If a driver couldn't be found (could be from PI or box CI)
// then implement using a LUT
RTLIL::Cell *cell = module->addLut(remap_name(stringf("$lut%s", mapped_cell->name)),
RTLIL::SigBit(module->wire(remap_name(a_bit.wire->name)), a_bit.offset),
RTLIL::SigBit(module->wire(remap_name(y_bit.wire->name)), y_bit.offset),
RTLIL::Cell *cell = module->addLut(Twine{remap_name(stringf("$lut%s", mapped_cell->name))},
RTLIL::SigBit(module->wire(rn(a_bit.wire->name)), a_bit.offset),
RTLIL::SigBit(module->wire(rn(y_bit.wire->name)), y_bit.offset),
RTLIL::Const::from_string("01"));
bit2sinks[cell->getPort(TW::A)].push_back(cell);
cell_stats[TW($lut)]++;
cell_stats[ID($lut)]++;
}
else
not2drivers[mapped_cell] = driver_lut;
@ -1354,7 +1368,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
}
if (mapped_cell->type == TW($lut)) {
RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
RTLIL::Cell *cell = module->addCell(rn(mapped_cell->name), mapped_cell->type_impl);
cell->parameters = mapped_cell->parameters;
cell->attributes = mapped_cell->attributes;
@ -1365,7 +1379,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
continue;
//log_assert(c.width == 1);
if (c.wire)
c.wire = module->wire(remap_name(c.wire->name));
c.wire = module->wire(rn(c.wire->name));
newsig.append(c);
}
cell->setPort(mapped_conn.first, newsig);
@ -1384,7 +1398,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
}
}
else {
RTLIL::Cell *existing_cell = module->cell(mapped_cell->name);
RTLIL::Cell *existing_cell = module->cell(mapped_cell->name.ref());
if (!existing_cell)
log_error("Cannot find existing box cell with name '%s' in original design.\n", mapped_cell);
@ -1392,28 +1406,28 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
SigBit I = mapped_cell->getPort(TW::i);
SigBit O = mapped_cell->getPort(TW::o);
if (I.wire)
I.wire = module->wire(remap_name(I.wire->name));
I.wire = module->wire(rn(I.wire->name));
log_assert(O.wire);
O.wire = module->wire(remap_name(O.wire->name));
O.wire = module->wire(rn(O.wire->name));
module->connect(O, I);
continue;
}
RTLIL::Module* box_module = design->module(existing_cell->type);
RTLIL::Module* box_module = design->module(existing_cell->type_impl);
log_assert(existing_cell->parameters.empty());
log_assert(mapped_cell->type == stringf("$__boxid%d", box_module->attributes.at(ID::abc9_box_id).as_int()));
mapped_cell->type_impl = existing_cell->type_impl;
RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
RTLIL::Cell *cell = module->addCell(rn(mapped_cell->name), mapped_cell->type_impl);
cell->parameters = existing_cell->parameters;
cell->attributes = existing_cell->attributes;
module->swap_names(cell, existing_cell);
auto jt = mapped_cell->connections_.find(ID(i));
auto jt = mapped_cell->connections_.find(TW::i);
log_assert(jt != mapped_cell->connections_.end());
SigSpec inputs = std::move(jt->second);
mapped_cell->connections_.erase(jt);
jt = mapped_cell->connections_.find(ID(o));
jt = mapped_cell->connections_.find(TW::o);
log_assert(jt != mapped_cell->connections_.end());
SigSpec outputs = std::move(jt->second);
mapped_cell->connections_.erase(jt);
@ -1424,7 +1438,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
// flop box, so that any (public) signal it drives will be
// preserved
SigBit old_q;
for (const auto &port_name : box_ports.at(existing_cell->type)) {
for (const auto &port_name : box_ports.at(existing_cell->type.ref())) {
RTLIL::Wire *w = box_module->wire(port_name);
log_assert(w);
if (!w->port_output)
@ -1434,7 +1448,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
old_q = existing_cell->getPort(port_name);
}
auto new_q = outputs[0];
new_q.wire = module->wire(remap_name(new_q.wire->name));
new_q.wire = module->wire(rn(new_q.wire->name));
module->connect(old_q, new_q);
}
else {
@ -1447,7 +1461,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
}
int input_count = 0, output_count = 0;
for (const auto &port_name : box_ports.at(existing_cell->type)) {
for (const auto &port_name : box_ports.at(existing_cell->type.ref())) {
RTLIL::Wire *w = box_module->wire(port_name);
log_assert(w);
@ -1467,7 +1481,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
continue;
//log_assert(c.width == 1);
if (c.wire)
c.wire = module->wire(remap_name(c.wire->name));
c.wire = module->wire(rn(c.wire->name));
newsig.append(c);
}
@ -1490,14 +1504,14 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
if (!conn.first.is_fully_const()) {
std::vector<RTLIL::SigChunk> chunks = conn.first.chunks();
for (auto &c : chunks)
c.wire = module->wire(remap_name(c.wire->name));
c.wire = module->wire(rn(c.wire->name));
conn.first = std::move(chunks);
}
if (!conn.second.is_fully_const()) {
std::vector<RTLIL::SigChunk> chunks = conn.second.chunks();
for (auto &c : chunks)
if (c.wire)
c.wire = module->wire(remap_name(c.wire->name));
c.wire = module->wire(rn(c.wire->name));
conn.second = std::move(chunks);
}
module->connect(conn);
@ -1513,7 +1527,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
RTLIL::Wire *wire = module->wire(port);
log_assert(wire);
RTLIL::Wire *remap_wire = module->wire(remap_name(port));
RTLIL::Wire *remap_wire = module->wire(rn(mapped_wire->name));
RTLIL::SigSpec signal(wire, remap_wire->start_offset-wire->start_offset, GetSize(remap_wire));
log_assert(GetSize(signal) >= GetSize(remap_wire));
@ -1552,7 +1566,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
log_assert(no_loops);
for (auto ii = toposort.sorted.rbegin(); ii != toposort.sorted.rend(); ii++) {
RTLIL::Cell *not_cell = mapped_mod->cell(*ii);
RTLIL::Cell *not_cell = mapped_mod->cell(refof(*ii));
log_assert(not_cell);
if (not_cell->type != TW($_NOT_))
continue;
@ -1564,8 +1578,8 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
RTLIL::SigBit y_bit = not_cell->getPort(TW::Y);
RTLIL::Const driver_mask;
a_bit.wire = module->wire(remap_name(a_bit.wire->name));
y_bit.wire = module->wire(remap_name(y_bit.wire->name));
a_bit.wire = module->wire(rn(a_bit.wire->name));
y_bit.wire = module->wire(rn(y_bit.wire->name));
auto jt = bit2sinks.find(a_bit);
if (jt == bit2sinks.end())
@ -1613,8 +1627,8 @@ clone_lut:
driver_lut->getPort(TW::A),
y_bit,
driver_mask);
for (auto &bit : cell->connections_.at(ID::A)) {
bit.wire = module->wire(remap_name(bit.wire->name));
for (auto &bit : cell->connections_.at(TW::A)) {
bit.wire = module->wire(rn(bit.wire->name));
bit2sinks[bit].push_back(cell);
}
}
@ -1681,7 +1695,7 @@ static void restore_zbufs(Design *design)
for (auto cell : to_remove) {
SigSpec sig_y = cell->getPort(TW::Y);
mod->addBuf(NEW_ID, Const(State::Sz, GetSize(sig_y)), sig_y);
mod->addBuf(NEW_TWINE, Const(State::Sz, GetSize(sig_y)), sig_y);
mod->remove(cell);
}
}

2
passes/techmap/abc_new.cc
View file

@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
std::vector<Module*> order_modules(Design *design, std::vector<Module *> modules)
{
std::set<Module *> modules_set(modules.begin(), modules.end());
using Order = IdString::compare_ptr_by_name<RTLIL::NamedObject>;
using Order = IdString::compare_ptr_by_name<RTLIL::Module>;
TopoSort<Module*, Order> sort;
for (auto m : modules) {

49
passes/techmap/booth.cc
View file

@ -132,14 +132,14 @@ struct BoothPassWorker {
// (y2_p1 & y2_n & y2_m1_n)
// )
twoi_n_o = module->NorGate(NEW_TWINE_SUFFIX(name),
module->AndGate(NEW_ID_SUFFIX(name), y2_p1_n, module->AndGate(NEW_TWINE_SUFFIX(name), y2_i, y2_m1_i)),
module->AndGate(NEW_ID_SUFFIX(name), y2_p1_i, module->AndGate(NEW_TWINE_SUFFIX(name), y2_n, y2_m1_n))
module->AndGate(NEW_TWINE_SUFFIX(name), y2_p1_n, module->AndGate(NEW_TWINE_SUFFIX(name), y2_i, y2_m1_i)),
module->AndGate(NEW_TWINE_SUFFIX(name), y2_p1_i, module->AndGate(NEW_TWINE_SUFFIX(name), y2_n, y2_m1_n))
);
// onei_n = ~(y2_m1_i ^ y2_i);
onei_n_o = module->XnorGate(NEW_TWINE_SUFFIX(name), y2_m1_i, y2_i);
// cori = (y2_m1_n | y2_n) & y2_p1_i;
cori_o = module->AndGate(NEW_ID_SUFFIX(name), module->OrGate(NEW_TWINE_SUFFIX(name), y2_m1_n, y2_n), y2_p1_i);
cori_o = module->AndGate(NEW_TWINE_SUFFIX(name), module->OrGate(NEW_TWINE_SUFFIX(name), y2_m1_n, y2_n), y2_p1_i);
}
//
@ -201,9 +201,10 @@ struct BoothPassWorker {
log_assert(sig_a.size() == sig_x.size());
log_assert(sig_a.size() == sig_y.size());
TwineRef src_ref = src.empty() ? Twine::Null : mod->design->twines.add(Twine{src});
for (int i = 0; i < sig_a.size(); i++)
mod->addFa(stringf("%s[%d]", name, i), sig_a[i], sig_b[i],
sig_c[i], sig_x[i], sig_y[i], src);
mod->addFa(Twine{stringf("%s[%d]", name, i)}, sig_a[i], sig_b[i],
sig_c[i], sig_x[i], sig_y[i], src_ref);
}
void run()
@ -431,7 +432,7 @@ struct BoothPassWorker {
// append the sign bits
if (is_signed) {
SigBit e = module->XorGate(NEW_ID, s_int[0], module->AndGate(NEW_ID, X.msb(), module->OrGate(NEW_TWINE, two_int[0], one_int[0])));
SigBit e = module->XorGate(NEW_TWINE, s_int[0], module->AndGate(NEW_TWINE, X.msb(), module->OrGate(NEW_TWINE, two_int[0], one_int[0])));
ppij_vec.append({module->NotGate(NEW_TWINE, e), e, e});
} else {
// append the sign bits
@ -465,7 +466,7 @@ struct BoothPassWorker {
one_int, two_int, s_int));
}
ppij_vec.append(!is_signed ? sb_int[0] : module->XorGate(NEW_ID, sb_int, module->AndGate(NEW_ID, X.msb(), module->OrGate(NEW_TWINE, two_int, one_int))));
ppij_vec.append(!is_signed ? sb_int[0] : module->XorGate(NEW_TWINE, sb_int, module->AndGate(NEW_TWINE, X.msb(), module->OrGate(NEW_TWINE, two_int, one_int))));
ppij_vec.append(State::S1);
}
@ -476,7 +477,7 @@ struct BoothPassWorker {
for (auto pp_row : aligned_pp) {
printf("PP_%d \t", pp_ix);
for (unsigned i = 0; i < pp_row.size(); i++)
printf("[%d] %s ", i, pp_row[i] == nullptr ? " 0 " : pp_row[i]->name.c_str());
printf("[%d] %s ", i, pp_row[i] == nullptr ? " 0 " : pp_row[i]->name.str().c_str());
printf("\n");
pp_ix++;
}
@ -504,7 +505,7 @@ struct BoothPassWorker {
ix++;
}
printf("\n");
printf("\tSign bit to add in: %s\n", sign_bit->name.c_str());
printf("\tSign bit to add in: %s\n", sign_bit->name.str().c_str());
pp_ix++;
}
@ -517,30 +518,30 @@ struct BoothPassWorker {
printf("CSA Tree column %d\n", i);
int ix = 0;
for (auto csa_elem : csa_tree) {
printf("\tCell %d %s type %s\n", ix, csa_elem->name.c_str(), csa_elem->type.c_str());
printf("\tCell %d %s type %s\n", ix, csa_elem->name.str().c_str(), csa_elem->type.str().c_str());
if (csa_elem->getPort(TW::A) == State::S0)
printf("\tA set to constant 0\n");
else if (csa_elem->getPort(TW::A) == State::S1)
printf("\tA set to constant 1\n");
else
printf("\tA driven by %s\n", csa_elem->getPort(TW::A).as_wire()->name.c_str());
printf("\tA driven by %s\n", csa_elem->getPort(TW::A).as_wire()->name.str().c_str());
if (csa_elem->getPort(TW::B) == State::S0)
printf("\tB set to constant 0\n");
else if (csa_elem->getPort(TW::B) == State::S1)
printf("\tB set to constant 1\n");
else
printf("\tB driven by %s\n", csa_elem->getPort(TW::B).as_wire()->name.c_str());
printf("\tB driven by %s\n", csa_elem->getPort(TW::B).as_wire()->name.str().c_str());
if (csa_elem->getPort(TW::C) == State::S0)
printf("\tC set to constant 0\n");
else if (csa_elem->getPort(TW::C) == State::S1)
printf("\tC set to constant 1\n");
else
printf("\tC driven by %s\n", csa_elem->getPort(TW::C).as_wire()->name.c_str());
printf("\tC driven by %s\n", csa_elem->getPort(TW::C).as_wire()->name.str().c_str());
printf("Carry out: %s\n", csa_elem->getPort(TW::X).as_wire()->name.c_str());
printf("Sum out: %s\n", csa_elem->getPort(TW::Y).as_wire()->name.c_str());
printf("Carry out: %s\n", csa_elem->getPort(TW::X).as_wire()->name.str().c_str());
printf("Sum out: %s\n", csa_elem->getPort(TW::Y).as_wire()->name.str().c_str());
ix++;
}
@ -569,7 +570,7 @@ struct BoothPassWorker {
}
for (auto c : carry_bits_to_add_to_next_column) {
#ifdef DEBUG_CSA
printf("\t Propagating column bit %s to column %d from column %d\n", c->name.c_str(), column_ix, column_ix - 1);
printf("\t Propagating column bit %s to column %d from column %d\n", c->name.str().c_str(), column_ix, column_ix - 1);
#endif
column_bits.append(c);
}
@ -579,7 +580,7 @@ struct BoothPassWorker {
#ifdef DEBUG_CSA
printf("Column %d Reducing %d bits\n", column_ix, column_bits.size());
for (auto b : column_bits) {
printf("\t %s\n", b->name.c_str());
printf("\t %s\n", b->name.str().c_str());
}
printf("\n");
#endif
@ -695,7 +696,7 @@ struct BoothPassWorker {
module->addBufGate(NEW_TWINE_SUFFIX(stringf("base_buf_%d_%d", cpa_id, n)), s_vec[0], result[0]);
#ifdef DEBUG_CPA
printf("CPA bit [%d] Cell %s IP 0 %s \n", n, buf->name.c_str(), s_vec[0]->name.c_str());
printf("CPA bit [%d] Cell %s IP 0 %s \n", n, buf->name.str().c_str(), s_vec[0]->name.str().c_str());
#endif
}
@ -710,8 +711,8 @@ struct BoothPassWorker {
module->connect(result[n], ha_op);
#ifdef DEBUG_CPA
printf("CPA bit [%d] Cell %s IPs [%s] [%s] \n", n, ha_cell->name.c_str(), s_vec[n]->name.c_str(),
c_vec[n - 1]->name.c_str());
printf("CPA bit [%d] Cell %s IPs [%s] [%s] \n", n, ha_cell->name.str().c_str(), s_vec[n]->name.str().c_str(),
c_vec[n - 1]->name.str().c_str());
#endif
}
@ -729,8 +730,8 @@ struct BoothPassWorker {
carry = carry_out;
#ifdef DEBUG_CPA
printf("CPA bit [%d] Cell %s IPs [%s] [%s] [%s]\n", n, fa_cell->name.c_str(), s_vec[n]->name.c_str(),
c_vec[n - 1]->name.c_str(), carry->name.c_str());
printf("CPA bit [%d] Cell %s IPs [%s] [%s] [%s]\n", n, fa_cell->name.str().c_str(), s_vec[n]->name.str().c_str(),
c_vec[n - 1]->name.str().c_str(), carry->name.str().c_str());
#endif
if (n + 1 < GetSize(result)) {
// Now make a half adder: c_vec[n] = carry
@ -756,8 +757,8 @@ struct BoothPassWorker {
);
carry = carry_out;
#ifdef DEBUG_CPA
printf("CPA bit [%d] Cell %s IPs [%s] [%s] [%s]\n", n, fa_cell->name.c_str(), s_vec[n]->name.c_str(),
c_vec[n - 1]->name.c_str(), carry->name.c_str());
printf("CPA bit [%d] Cell %s IPs [%s] [%s] [%s]\n", n, fa_cell->name.str().c_str(), s_vec[n]->name.str().c_str(),
c_vec[n - 1]->name.str().c_str(), carry->name.str().c_str());
#endif
}
}

12
passes/techmap/bufnorm.cc
View file

@ -271,7 +271,7 @@ struct BufnormPass : public Pass {
SigMap sigmap(module);
module->new_connections({});
dict<pair<IdString, SigSpec>, Cell*> old_buffers;
dict<pair<TwineRef, SigSpec>, Cell*> old_buffers;
{
vector<Cell*> old_dup_buffers;
@ -285,7 +285,7 @@ struct BufnormPass : public Pass {
for (int i = 0; i < GetSize(insig) && i < GetSize(outsig); i++)
sigmap.add(insig[i], outsig[i]);
pair<IdString,Wire*> key(cell->type, outsig.as_wire());
pair<TwineRef,Wire*> key(cell->type_impl, outsig.as_wire());
if (old_buffers.count(key))
old_dup_buffers.push_back(cell);
else
@ -432,9 +432,9 @@ struct BufnormPass : public Pass {
return mapped_bits.at(bit);
};
auto make_buffer_f = [&](IdString type, const SigSpec &src, const SigSpec &dst)
auto make_buffer_f = [&](TwineRef type, const SigSpec &src, const SigSpec &dst)
{
auto it = old_buffers.find(pair<IdString, SigSpec>(type, dst));
auto it = old_buffers.find(pair<TwineRef, SigSpec>(type, dst));
if (it != old_buffers.end())
{
@ -488,11 +488,11 @@ struct BufnormPass : public Pass {
}
} else {
if (bits_mode) {
IdString celltype = pos_mode ? TW($pos) : buf_mode ? TW($buf) : TW($_BUF_);
TwineRef celltype = pos_mode ? TW($pos) : buf_mode ? TW($buf) : TW($_BUF_);
for (int i = 0; i < GetSize(insig) && i < GetSize(outsig); i++)
make_buffer_f(celltype, insig[i], outsig[i]);
} else {
IdString celltype = pos_mode ? TW($pos) : buf_mode ? TW($buf) :
TwineRef celltype = pos_mode ? TW($pos) : buf_mode ? TW($buf) :
GetSize(outsig) == 1 ? TW($_BUF_) : TW($buf);
make_buffer_f(celltype, insig, outsig);
}

12
passes/techmap/cellmatch.cc
View file

@ -274,27 +274,27 @@ struct CellmatchPass : Pass {
log("Module %s matches %s\n", m, target.module);
// Add target.module to map_design ("$cellmatch")
// as a techmap rule to match m and replace it with target.module
Module *map = map_design->addModule(stringf("\\_60_%s_%s", m, target.module));
Cell *cell = map->addCell(ID::_TECHMAP_REPLACE_, target.module->name);
Module *map = map_design->addModule(map_design->twines.add(std::string{stringf("\\_60_%s_%s", m, target.module)}));
Cell *cell = map->addCell(TW::_TECHMAP_REPLACE_, Twine{target.module->name.str()});
map->attributes[ID(techmap_celltype)] = m->name.str();
for (int i = 0; i < outputs.size(); i++) {
log_assert(outputs[i].is_wire());
Wire *w = map->addWire(outputs[i].wire->name, 1);
Wire *w = map->addWire(Twine{outputs[i].wire->name.str()}, 1);
w->port_id = outputs[i].wire->port_id;
w->port_output = true;
log_assert(target_outputs[output_map[i]].is_wire());
cell->setPort(target_outputs[output_map[i]].wire->name, w);
cell->setPort(map_design->twines.add(std::string{target_outputs[output_map[i]].wire->name.str()}), w);
}
for (int i = 0; i < inputs.size(); i++) {
log_assert(inputs[i].is_wire());
Wire *w = map->addWire(inputs[i].wire->name, 1);
Wire *w = map->addWire(Twine{inputs[i].wire->name.str()}, 1);
w->port_id = inputs[i].wire->port_id;
w->port_input = true;
log_assert(target_inputs[input_map[i]].is_wire());
cell->setPort(target_inputs[input_map[i]].wire->name, w);
cell->setPort(map_design->twines.add(std::string{target_inputs[input_map[i]].wire->name.str()}), w);
}
map->fixup_ports();

59
passes/techmap/clkbufmap.cc
View file

@ -117,17 +117,24 @@ struct ClkbufmapPass : public Pass {
log_error("Either the -buf option or -inpad option is required.\n");
// Cell type, port name, bit index.
pool<pair<IdString, pair<IdString, int>>> sink_ports;
pool<pair<IdString, pair<IdString, int>>> buf_ports;
dict<pair<IdString, pair<IdString, int>>, pair<IdString, int>> inv_ports_out;
dict<pair<IdString, pair<IdString, int>>, pair<IdString, int>> inv_ports_in;
pool<pair<TwineRef, pair<TwineRef, int>>> sink_ports;
pool<pair<TwineRef, pair<TwineRef, int>>> buf_ports;
dict<pair<TwineRef, pair<TwineRef, int>>, pair<TwineRef, int>> inv_ports_out;
dict<pair<TwineRef, pair<TwineRef, int>>, pair<TwineRef, int>> inv_ports_in;
// If true, use both ther -buf and -inpad cell for input ports that are clocks.
bool buffer_inputs = true;
Module *inpad_mod = design->module(RTLIL::escape_id(inpad_celltype));
TwineRef buf_celltype_ref = design->twines.add(Twine{RTLIL::escape_id(buf_celltype)});
TwineRef buf_portname_ref = design->twines.add(Twine{RTLIL::escape_id(buf_portname)});
TwineRef buf_portname2_ref = design->twines.add(Twine{RTLIL::escape_id(buf_portname2)});
TwineRef inpad_celltype_ref = design->twines.add(Twine{RTLIL::escape_id(inpad_celltype)});
TwineRef inpad_portname_ref = design->twines.add(Twine{RTLIL::escape_id(inpad_portname)});
TwineRef inpad_portname2_ref = design->twines.add(Twine{RTLIL::escape_id(inpad_portname2)});
Module *inpad_mod = design->module(inpad_celltype_ref);
if (inpad_mod) {
Wire *buf_wire = inpad_mod->wire(RTLIL::escape_id(buf_portname));
Wire *buf_wire = inpad_mod->wire(buf_portname_ref);
if (buf_wire && buf_wire->get_bool_attribute(ID::clkbuf_driver))
buffer_inputs = false;
}
@ -145,16 +152,16 @@ struct ClkbufmapPass : public Pass {
auto wire = module->wire(port);
if (wire->get_bool_attribute(ID::clkbuf_driver))
for (int i = 0; i < GetSize(wire); i++)
buf_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(RTLIL::IdString(wire->name), i)));
buf_ports.insert(make_pair(module->name.ref(), make_pair(wire->name.ref(), i)));
if (wire->get_bool_attribute(ID::clkbuf_sink))
for (int i = 0; i < GetSize(wire); i++)
sink_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(RTLIL::IdString(wire->name), i)));
sink_ports.insert(make_pair(module->name.ref(), make_pair(wire->name.ref(), i)));
auto it = wire->attributes.find(ID::clkbuf_inv);
if (it != wire->attributes.end()) {
IdString in_name = RTLIL::escape_id(it->second.decode_string());
TwineRef in_name = design->twines.add(Twine{RTLIL::escape_id(it->second.decode_string())});
for (int i = 0; i < GetSize(wire); i++) {
inv_ports_out[make_pair(RTLIL::IdString(module->name), make_pair(RTLIL::IdString(wire->name), i))] = make_pair(in_name, i);
inv_ports_in[make_pair(RTLIL::IdString(module->name), make_pair(in_name, i))] = make_pair(RTLIL::IdString(wire->name), i);
inv_ports_out[make_pair(module->name.ref(), make_pair(wire->name.ref(), i))] = make_pair(in_name, i);
inv_ports_in[make_pair(module->name.ref(), make_pair(in_name, i))] = make_pair(wire->name.ref(), i);
}
}
}
@ -171,14 +178,14 @@ struct ClkbufmapPass : public Pass {
for (auto cell : module->cells())
for (auto port : cell->connections())
for (int i = 0; i < port.second.size(); i++)
if (sink_ports.count(make_pair(cell->type, make_pair(port.first, i))))
if (sink_ports.count(make_pair(cell->type_impl, make_pair(port.first, i))))
sink_wire_bits.insert(sigmap(port.second[i]));
// Second, collect ones that already have a clock buffer.
for (auto cell : module->cells())
for (auto port : cell->connections())
for (int i = 0; i < port.second.size(); i++)
if (buf_ports.count(make_pair(cell->type, make_pair(port.first, i))))
if (buf_ports.count(make_pair(cell->type_impl, make_pair(port.first, i))))
buf_wire_bits.insert(sigmap(port.second[i]));
// Third, propagate tags through inverters.
@ -188,7 +195,7 @@ struct ClkbufmapPass : public Pass {
for (auto cell : module->cells())
for (auto port : cell->connections())
for (int i = 0; i < port.second.size(); i++) {
auto it = inv_ports_out.find(make_pair(cell->type, make_pair(port.first, i)));
auto it = inv_ports_out.find(make_pair(cell->type_impl, make_pair(port.first, i)));
auto bit = sigmap(port.second[i]);
// If output of an inverter is connected to a sink, mark it as buffered,
// and request a buffer on the inverter's input instead.
@ -200,7 +207,7 @@ struct ClkbufmapPass : public Pass {
}
// If input of an inverter is marked as already-buffered,
// mark its output already-buffered as well.
auto it2 = inv_ports_in.find(make_pair(cell->type, make_pair(port.first, i)));
auto it2 = inv_ports_in.find(make_pair(cell->type_impl, make_pair(port.first, i)));
if (it2 != inv_ports_in.end() && buf_wire_bits.count(bit)) {
auto other_bit = sigmap(cell->getPort(it2->second.first)[it2->second.second]);
if (!buf_wire_bits.count(other_bit)) {
@ -236,7 +243,7 @@ struct ClkbufmapPass : public Pass {
// some buffer higher up in the hierarchy.
if (wire->port_output)
for (int i = 0; i < GetSize(wire); i++)
buf_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(RTLIL::IdString(wire->name), i)));
buf_ports.insert(make_pair(module->name.ref(), make_pair(wire->name.ref(), i)));
continue;
}
@ -249,7 +256,7 @@ struct ClkbufmapPass : public Pass {
if (buf_wire_bits.count(mapped_wire_bit)) {
// Already buffered downstream. If this is an output, mark it.
if (wire->port_output)
buf_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(RTLIL::IdString(wire->name), i)));
buf_ports.insert(make_pair(module->name.ref(), make_pair(wire->name.ref(), i)));
} else if (!sink_wire_bits.count(mapped_wire_bit)) {
// Nothing to do.
} else if (driven_wire_bits.count(wire_bit) || (wire->port_input && module->get_bool_attribute(ID::top))) {
@ -261,22 +268,22 @@ struct ClkbufmapPass : public Pass {
bool is_input = wire->port_input && !inpad_celltype.empty() && module->get_bool_attribute(ID::top);
if (!buf_celltype.empty() && (!is_input || buffer_inputs)) {
log("Inserting %s on %s.%s[%d].\n", buf_celltype, module, wire, i);
cell = module->addCell(NEW_TWINE, RTLIL::escape_id(buf_celltype));
cell = module->addCell(NEW_TWINE, buf_celltype_ref);
iwire = module->addWire(NEW_TWINE);
cell->setPort(RTLIL::escape_id(buf_portname), mapped_wire_bit);
cell->setPort(RTLIL::escape_id(buf_portname2), iwire);
cell->setPort(buf_portname_ref, mapped_wire_bit);
cell->setPort(buf_portname2_ref, iwire);
}
if (is_input) {
log("Inserting %s on %s.%s[%d].\n", inpad_celltype, module, wire, i);
RTLIL::Cell *cell2 = module->addCell(NEW_TWINE, RTLIL::escape_id(inpad_celltype));
RTLIL::Cell *cell2 = module->addCell(NEW_TWINE, inpad_celltype_ref);
if (iwire) {
cell2->setPort(RTLIL::escape_id(inpad_portname), iwire);
cell2->setPort(inpad_portname_ref, iwire);
} else {
cell2->setPort(RTLIL::escape_id(inpad_portname), mapped_wire_bit);
cell2->setPort(inpad_portname_ref, mapped_wire_bit);
cell = cell2;
}
iwire = module->addWire(NEW_TWINE);
cell2->setPort(RTLIL::escape_id(inpad_portname2), iwire);
cell2->setPort(inpad_portname2_ref, iwire);
}
if (iwire)
buffered_bits[mapped_wire_bit] = make_pair(cell, iwire);
@ -288,7 +295,7 @@ struct ClkbufmapPass : public Pass {
// A clock input in a submodule -- mark it, let higher level
// worry about it.
if (wire->port_input)
sink_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(RTLIL::IdString(wire->name), i)));
sink_ports.insert(make_pair(module->name.ref(), make_pair(wire->name.ref(), i)));
}
}
if (!input_bits.empty()) {
@ -320,7 +327,7 @@ struct ClkbufmapPass : public Pass {
SigBit wire_bit(wire, i);
SigBit mapped_wire_bit = sigmap(wire_bit);
if (buffered_bits.count(mapped_wire_bit))
buf_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(RTLIL::IdString(wire->name), i)));
buf_ports.insert(make_pair(module->name.ref(), make_pair(wire->name.ref(), i)));
}
}

47
passes/techmap/extract.cc
View file

@ -127,7 +127,7 @@ public:
for (auto &conn : needleCell->connections())
{
RTLIL::SigSpec needleSig = conn.second;
RTLIL::SigSpec haystackSig = haystackCell->getPort(portMapping.at(conn.first.str()));
RTLIL::SigSpec haystackSig = haystackCell->getPort(haystackCell->module->design->twines.add(std::string{portMapping.at(needleCell->module->design->twines.str(conn.first))}));
for (int i = 0; i < min(needleSig.size(), haystackSig.size()); i++) {
RTLIL::Wire *needleWire = needleSig[i].wire, *haystackWire = haystackSig[i].wire;
@ -153,14 +153,15 @@ bool module2graph(SubCircuit::Graph &graph, RTLIL::Module *mod, bool constports,
{
SigMap sigmap(mod);
std::map<RTLIL::SigBit, bit_ref_t> sig_bit_ref;
auto &tw = mod->design->twines;
if (sel && !sel->selected(mod)) {
log(" Skipping module %s as it is not selected.\n", design->twines.unescaped_str(mod->name));
log(" Skipping module %s as it is not selected.\n", mod->name.unescaped());
return false;
}
if (mod->processes.size() > 0) {
log(" Skipping module %s as it contains unprocessed processes.\n", design->twines.unescaped_str(mod->name));
log(" Skipping module %s as it contains unprocessed processes.\n", mod->name.unescaped());
return false;
}
@ -206,9 +207,9 @@ bool module2graph(SubCircuit::Graph &graph, RTLIL::Module *mod, bool constports,
for (auto &conn : cell->connections())
{
graph.createPort(cell->name.str(), conn.first.str(), conn.second.size());
graph.createPort(cell->name.str(), tw.str(conn.first), conn.second.size());
if (split && split->count(std::pair<RTLIL::IdString, RTLIL::IdString>(cell->type, conn.first)) > 0)
if (split && split->count(std::pair<RTLIL::IdString, RTLIL::IdString>(IdString(cell->type.str()), IdString(tw.str(conn.first)))) > 0)
continue;
RTLIL::SigSpec conn_sig = conn.second;
@ -224,9 +225,9 @@ bool module2graph(SubCircuit::Graph &graph, RTLIL::Module *mod, bool constports,
if (bit == RTLIL::State::S0) node = "$const$0";
if (bit == RTLIL::State::S1) node = "$const$1";
if (bit == RTLIL::State::Sz) node = "$const$z";
graph.createConnection(cell->name.str(), conn.first.str(), i, node, "\\Y", 0);
graph.createConnection(cell->name.str(), tw.str(conn.first), i, node, "\\Y", 0);
} else
graph.createConstant(cell->name.str(), conn.first.str(), i, int(bit.data));
graph.createConstant(cell->name.str(), tw.str(conn.first), i, int(bit.data));
continue;
}
@ -239,12 +240,12 @@ bool module2graph(SubCircuit::Graph &graph, RTLIL::Module *mod, bool constports,
if (sig_bit_ref.count(bit) == 0) {
bit_ref_t &bit_ref = sig_bit_ref[bit];
bit_ref.cell = cell->name.str();
bit_ref.port = conn.first.str();
bit_ref.port = tw.str(conn.first);
bit_ref.bit = i;
}
bit_ref_t &bit_ref = sig_bit_ref[bit];
graph.createConnection(bit_ref.cell, bit_ref.port, bit_ref.bit, cell->name.str(), conn.first.str(), i);
graph.createConnection(bit_ref.cell, bit_ref.port, bit_ref.bit, cell->name.str(), tw.str(conn.first), i);
}
}
}
@ -289,16 +290,17 @@ bool module2graph(SubCircuit::Graph &graph, RTLIL::Module *mod, bool constports,
RTLIL::Cell *replace(RTLIL::Module *needle, RTLIL::Module *haystack, SubCircuit::Solver::Result &match)
{
SigMap sigmap(needle);
SigSet<std::pair<RTLIL::IdString, int>> sig2port;
SigSet<std::pair<TwineRef, int>> sig2port;
auto &tw = needle->design->twines;
// create new cell
RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name, autoidx++), needle->name);
RTLIL::Cell *cell = haystack->addCell(Twine{stringf("$extract$%s$%d", needle->name, autoidx++)}, Twine{needle->name.str()});
// create cell ports
for (auto wire : needle->wires()) {
if (wire->port_id > 0) {
for (int i = 0; i < wire->width; i++)
sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair<RTLIL::IdString, int>(wire->name, i));
sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair<TwineRef, int>(wire->meta_->name, i));
cell->setPort(wire->meta_->name, RTLIL::SigSpec(RTLIL::State::Sz, wire->width));
}
}
@ -315,10 +317,10 @@ RTLIL::Cell *replace(RTLIL::Module *needle, RTLIL::Module *haystack, SubCircuit:
for (auto &conn : needle_cell->connections()) {
RTLIL::SigSpec sig = sigmap(conn.second);
if (mapping.portMapping.count(conn.first.str()) > 0 && sig2port.has(sigmap(sig))) {
if (mapping.portMapping.count(tw.str(conn.first)) > 0 && sig2port.has(sigmap(sig))) {
for (int i = 0; i < sig.size(); i++)
for (auto &port : sig2port.find(sig[i])) {
RTLIL::SigSpec bitsig = haystack_cell->getPort(mapping.portMapping[conn.first.str()]).extract(i, 1);
RTLIL::SigSpec bitsig = haystack_cell->getPort(haystack_cell->module->design->twines.add(std::string{mapping.portMapping[tw.str(conn.first)]})).extract(i, 1);
RTLIL::SigSpec new_sig = cell->getPort(port.first);
new_sig.replace(port.second, bitsig);
cell->setPort(port.first, new_sig);
@ -674,7 +676,7 @@ struct ExtractPass : public Pass {
}
RTLIL::Cell *new_cell = replace(needle_map.at(result.needleGraphId), haystack_map.at(result.haystackGraphId), result);
design->select(haystack_map.at(result.haystackGraphId), new_cell);
log(" new cell: %s\n", new_cell->module->design->twines.str(cell->meta_->name));
log(" new cell: %s\n", new_cell->name.str().c_str());
}
}
}
@ -691,12 +693,12 @@ struct ExtractPass : public Pass {
for (auto &result: results)
{
log("\nFrequent SubCircuit with %d nodes and %d matches:\n", int(result.nodes.size()), result.totalMatchesAfterLimits);
log(" primary match in %s:", design->twines.unescaped_str(haystack_map.at(result.graphId)->name));
log(" primary match in %s:", haystack_map.at(result.graphId)->name.unescaped());
for (auto &node : result.nodes)
log(" %s", RTLIL::unescape_id(node.nodeId));
log("\n");
for (auto &it : result.matchesPerGraph)
log(" matches in %s: %d\n", design->twines.unescaped_str(haystack_map.at(it.first)->name), it.second);
log(" matches in %s: %d\n", haystack_map.at(it.first)->name.unescaped(), it.second);
RTLIL::Module *mod = haystack_map.at(result.graphId);
std::set<RTLIL::Cell*> cells;
@ -715,13 +717,10 @@ struct ExtractPass : public Pass {
wires.insert(chunk.wire);
}
RTLIL::Module *newMod = new RTLIL::Module;
newMod->design = map;
newMod->name = stringf("\\needle%05d_%s_%dx", needleCounter++, design->twines.unescaped_str(haystack_map.at(result.graphId)->name), result.totalMatchesAfterLimits);
map->add(newMod);
RTLIL::Module *newMod = map->addModule(map->twines.add(stringf("\\needle%05d_%s_%dx", needleCounter++, haystack_map.at(result.graphId)->name.unescaped(), result.totalMatchesAfterLimits)));
for (auto wire : wires) {
RTLIL::Wire *newWire = newMod->addWire(wire->name, wire->width);
RTLIL::Wire *newWire = newMod->addWire(Twine{wire->name.str()}, wire->width);
newWire->port_input = true;
newWire->port_output = true;
}
@ -729,13 +728,13 @@ struct ExtractPass : public Pass {
newMod->fixup_ports();
for (auto cell : cells) {
RTLIL::Cell *newCell = newMod->addCell(cell->name, cell->type);
RTLIL::Cell *newCell = newMod->addCell(Twine{cell->name.str()}, Twine{cell->type.str()});
newCell->parameters = cell->parameters;
for (auto &conn : cell->connections()) {
std::vector<SigChunk> chunks = sigmap(conn.second);
for (auto &chunk : chunks)
if (chunk.wire != nullptr)
chunk.wire = newMod->wire(chunk.wire->name);
chunk.wire = newMod->wire(map->twines.add(Twine{chunk.wire->name.str()}));
newCell->setPort(conn.first, chunks);
}
}

12
passes/techmap/extract_counter.cc
View file

@ -535,11 +535,9 @@ void counter_worker(
string count_reg_src = port_wire->get_src_attribute().c_str();
if(port_wire->attributes.find(ID(COUNT_EXTRACT)) != port_wire->attributes.end())
{
pool<string> sa = port_wire->get_strpool_attribute(ID(COUNT_EXTRACT));
string extract_value;
if(sa.size() >= 1)
string extract_value = port_wire->get_string_attribute(ID(COUNT_EXTRACT));
if(!extract_value.empty())
{
extract_value = *sa.begin();
log(" Signal %s declared at %s has COUNT_EXTRACT = %s\n",
port_wire,
count_reg_src.c_str(),
@ -611,7 +609,7 @@ void counter_worker(
}
//Get new cell name
string countname = string("$COUNTx$") + design->twines.unescaped_str(extract.rwire->name);
string countname = string("$COUNTx$") + extract.rwire->name.unescaped();
//Wipe all of the old connections to the ALU
cell->unsetPort(TW::A);
@ -697,7 +695,7 @@ void counter_worker(
//Hook up any parallel outputs
for(auto load : extract.pouts)
{
log(" Counter has parallel output to cell %s port %s\n", load.cell->module->design->twines.str(cell->meta_->name), design->twines.unescaped_str(load.port));
log(" Counter has parallel output to cell %s port %s\n", load.cell->module->design->twines.str(cell->meta_->name), load.cell->module->design->twines.unescaped_str(load.port));
}
if(extract.has_pout)
{
@ -894,7 +892,7 @@ struct ExtractCounterPass : public Pass {
for(auto cpair : cells_to_rename)
{
//log("Renaming cell %s to %s\n", cpair.first, cpair.second);
module->rename(cpair.first, cpair.second);
module->rename(cpair.first, module->design->twines.add(std::string{cpair.second}));
}
}

12
passes/techmap/extractinv.cc
View file

@ -80,6 +80,10 @@ struct ExtractinvPass : public Pass {
if (inv_celltype.empty())
log_error("The -inv option is required.\n");
TwineRef inv_celltype_ref = design->twines.add(std::string{RTLIL::escape_id(inv_celltype)});
TwineRef inv_portname_ref = design->twines.add(std::string{RTLIL::escape_id(inv_portname)});
TwineRef inv_portname2_ref = design->twines.add(std::string{RTLIL::escape_id(inv_portname2)});
for (auto module : design->selected_modules())
{
for (auto cell : module->selected_cells())
@ -100,7 +104,7 @@ struct ExtractinvPass : public Pass {
continue;
SigSpec sig = port.second;
if (it2->second.size() != sig.size())
log_error("The inversion parameter needs to be the same width as the port (%s.%s port %s parameter %s)", design->twines.unescaped_str(module->name), cell->type.unescaped(), design->twines.unescaped_str(port.first), design->twines.unescaped_str(param_name));
log_error("The inversion parameter needs to be the same width as the port (%s.%s port %s parameter %s)", module->name.unescaped(), cell->type.unescaped(), design->twines.unescaped_str(port.first), RTLIL::unescape_id(param_name));
RTLIL::Const invmask = it2->second;
cell->parameters.erase(param_name);
if (invmask.is_fully_zero())
@ -108,9 +112,9 @@ struct ExtractinvPass : public Pass {
Wire *iwire = module->addWire(NEW_TWINE, sig.size());
for (int i = 0; i < sig.size(); i++)
if (invmask[i] == State::S1) {
RTLIL::Cell *icell = module->addCell(NEW_TWINE, RTLIL::escape_id(inv_celltype));
icell->setPort(RTLIL::escape_id(inv_portname), SigSpec(iwire, i));
icell->setPort(RTLIL::escape_id(inv_portname2), sig[i]);
RTLIL::Cell *icell = module->addCell(NEW_TWINE, inv_celltype_ref);
icell->setPort(inv_portname_ref, SigSpec(iwire, i));
icell->setPort(inv_portname2_ref, sig[i]);
log("Inserting %s on %s.%s.%s[%d].\n", inv_celltype, module, cell->type.unescaped(), design->twines.unescaped_str(port.first), i);
sig[i] = SigBit(iwire, i);
}

4
passes/techmap/flowmap.cc
View file

@ -1376,10 +1376,10 @@ struct FlowmapWorker
auto gate_origin = node_origins[gate_node];
if (gate_origin.cell->getPort(gate_origin.port).size() == 1)
log(" Packing %s.%s.%s (%s).\n",
module, gate_origin.cell, gate_module->design->twines.str(origin.port).c_str(), log_signal(gate_node));
module, gate_origin.cell, gate_origin.cell->module->design->twines.str(gate_origin.port).c_str(), log_signal(gate_node));
else
log(" Packing %s.%s.%s [%d] (%s).\n",
module, gate_origin.cell, gate_module->design->twines.str(origin.port).c_str(), gate_origin.offset, log_signal(gate_node));
module, gate_origin.cell, gate_origin.cell->module->design->twines.str(gate_origin.port).c_str(), gate_origin.offset, log_signal(gate_node));
}
vector<RTLIL::SigBit> input_nodes(lut_edges_bw[node].begin(), lut_edges_bw[node].end());

64
passes/techmap/iopadmap.cc
View file

@ -202,7 +202,7 @@ struct IopadmapPass : public Pass {
// Recursively collect list of (module, port, bit) triples that already have buffers.
pool<pair<IdString, pair<IdString, int>>> buf_ports;
pool<pair<TwineRef, pair<TwineRef, int>>> buf_ports;
// Process submodules before module using them.
std::vector<Module *> modules_sorted;
@ -225,7 +225,7 @@ struct IopadmapPass : public Pass {
for (auto cell : module->cells())
for (auto port : cell->connections())
for (int i = 0; i < port.second.size(); i++)
if (buf_ports.count(make_pair(cell->type, make_pair(port.first, i))))
if (buf_ports.count(make_pair(cell->type_impl, make_pair(port.first, i))))
buf_bits.insert(sigmap(port.second[i]));
// Now fill buf_ports.
@ -233,7 +233,7 @@ struct IopadmapPass : public Pass {
if (wire->port_input || wire->port_output)
for (int i = 0; i < GetSize(wire); i++)
if (buf_bits.count(sigmap(SigBit(wire, i)))) {
buf_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(RTLIL::IdString(wire->name), i)));
buf_ports.insert(make_pair(module->name.ref(), make_pair(wire->name.ref(), i)));
log("Marking already mapped port: %s.%s[%d].\n", module, wire, i);
}
}
@ -242,7 +242,7 @@ struct IopadmapPass : public Pass {
for (auto module : design->selected_modules())
{
dict<Wire *, dict<int, pair<Cell *, IdString>>> rewrite_bits;
dict<Wire *, dict<int, pair<Cell *, TwineRef>>> rewrite_bits;
dict<SigSig, pool<int>> remove_conns;
if (!toutpad_celltype.empty() || !tinoutpad_celltype.empty())
@ -293,7 +293,7 @@ struct IopadmapPass : public Pass {
SigBit wire_bit(wire, i);
Cell *tbuf_cell = nullptr;
if (buf_ports.count(make_pair(RTLIL::IdString(module->name), make_pair(RTLIL::IdString(wire->name), i))))
if (buf_ports.count(make_pair(module->name.ref(), make_pair(wire->name.ref(), i))))
continue;
if (tbuf_bits.count(wire_bit))
@ -330,37 +330,37 @@ struct IopadmapPass : public Pass {
log("Mapping port %s.%s[%d] using %s.\n", module, wire, i, tinoutpad_celltype);
Cell *cell = module->addCell(
module->uniquify(stringf("$iopadmap$%s.%s[%d]", module, wire, i)),
RTLIL::escape_id(tinoutpad_celltype));
module->uniquify(Twine{stringf("$iopadmap$%s.%s[%d]", module, wire, i)}),
module->design->twines.add(Twine{RTLIL::escape_id(tinoutpad_celltype)}));
if (tinoutpad_neg_oe)
en_sig = module->NotGate(NEW_TWINE, en_sig);
cell->setPort(RTLIL::escape_id(tinoutpad_portname_oe), en_sig);
cell->setPort(module->design->twines.add(Twine{RTLIL::escape_id(tinoutpad_portname_oe)}), en_sig);
cell->attributes[ID::keep] = RTLIL::Const(1);
if (tbuf_cell) {
module->remove(tbuf_cell);
cell->setPort(RTLIL::escape_id(tinoutpad_portname_o), wire_bit);
cell->setPort(RTLIL::escape_id(tinoutpad_portname_i), data_sig);
cell->setPort(module->design->twines.add(Twine{RTLIL::escape_id(tinoutpad_portname_o)}), wire_bit);
cell->setPort(module->design->twines.add(Twine{RTLIL::escape_id(tinoutpad_portname_i)}), data_sig);
} else if (is_driven) {
cell->setPort(RTLIL::escape_id(tinoutpad_portname_i), wire_bit);
cell->setPort(module->design->twines.add(Twine{RTLIL::escape_id(tinoutpad_portname_i)}), wire_bit);
} else {
cell->setPort(RTLIL::escape_id(tinoutpad_portname_o), wire_bit);
cell->setPort(RTLIL::escape_id(tinoutpad_portname_i), data_sig);
cell->setPort(module->design->twines.add(Twine{RTLIL::escape_id(tinoutpad_portname_o)}), wire_bit);
cell->setPort(module->design->twines.add(Twine{RTLIL::escape_id(tinoutpad_portname_i)}), data_sig);
}
if (!tinoutpad_portname_pad.empty())
rewrite_bits[wire][i] = make_pair(cell, RTLIL::escape_id(tinoutpad_portname_pad));
rewrite_bits[wire][i] = make_pair(cell, module->design->twines.add(Twine{RTLIL::escape_id(tinoutpad_portname_pad)}));
} else {
log("Mapping port %s.%s[%d] using %s.\n", module, wire, i, toutpad_celltype);
Cell *cell = module->addCell(
module->uniquify(stringf("$iopadmap$%s.%s[%d]", module, wire, i)),
RTLIL::escape_id(toutpad_celltype));
module->uniquify(Twine{stringf("$iopadmap$%s.%s[%d]", module, wire, i)}),
module->design->twines.add(Twine{RTLIL::escape_id(toutpad_celltype)}));
if (toutpad_neg_oe)
en_sig = module->NotGate(NEW_TWINE, en_sig);
cell->setPort(RTLIL::escape_id(toutpad_portname_oe), en_sig);
cell->setPort(RTLIL::escape_id(toutpad_portname_i), data_sig);
cell->setPort(module->design->twines.add(Twine{RTLIL::escape_id(toutpad_portname_oe)}), en_sig);
cell->setPort(module->design->twines.add(Twine{RTLIL::escape_id(toutpad_portname_i)}), data_sig);
cell->attributes[ID::keep] = RTLIL::Const(1);
if (tbuf_cell) {
@ -368,9 +368,9 @@ struct IopadmapPass : public Pass {
module->connect(wire_bit, data_sig);
}
if (!toutpad_portname_pad.empty())
rewrite_bits[wire][i] = make_pair(cell, RTLIL::escape_id(toutpad_portname_pad));
rewrite_bits[wire][i] = make_pair(cell, module->design->twines.add(Twine{RTLIL::escape_id(toutpad_portname_pad)}));
}
buf_ports.insert(make_pair(RTLIL::IdString(module->name), make_pair(RTLIL::IdString(wire->name), i)));
buf_ports.insert(make_pair(module->name.ref(), make_pair(wire->name.ref(), i)));
}
}
}
@ -384,7 +384,7 @@ struct IopadmapPass : public Pass {
pool<int> skip_bit_indices;
for (int i = 0; i < GetSize(wire); i++)
if (buf_ports.count(make_pair(RTLIL::IdString(module->name), make_pair(RTLIL::IdString(wire->name), i))))
if (buf_ports.count(make_pair(module->name.ref(), make_pair(wire->name.ref(), i))))
skip_bit_indices.insert(i);
if (GetSize(wire) == GetSize(skip_bit_indices))
@ -436,12 +436,12 @@ struct IopadmapPass : public Pass {
SigBit wire_bit(wire, i);
RTLIL::Cell *cell = module->addCell(
module->uniquify(stringf("$iopadmap$%s.%s", design->twines.unescaped_str(module->name), design->twines.unescaped_str(wire->name))),
RTLIL::escape_id(celltype));
cell->setPort(RTLIL::escape_id(portname_int), wire_bit);
module->uniquify(Twine{stringf("$iopadmap$%s.%s", module->name.unescaped(), wire->name.unescaped())}),
module->design->twines.add(Twine{RTLIL::escape_id(celltype)}));
cell->setPort(module->design->twines.add(Twine{RTLIL::escape_id(portname_int)}), wire_bit);
if (!portname_pad.empty())
rewrite_bits[wire][i] = make_pair(cell, RTLIL::escape_id(portname_pad));
rewrite_bits[wire][i] = make_pair(cell, module->design->twines.add(Twine{RTLIL::escape_id(portname_pad)}));
if (!widthparam.empty())
cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1);
if (!nameparam.empty())
@ -452,23 +452,23 @@ struct IopadmapPass : public Pass {
else
{
RTLIL::Cell *cell = module->addCell(
module->uniquify(stringf("$iopadmap$%s.%s", design->twines.unescaped_str(module->name), design->twines.unescaped_str(wire->name))),
RTLIL::escape_id(celltype));
cell->setPort(RTLIL::escape_id(portname_int), RTLIL::SigSpec(wire));
module->uniquify(Twine{stringf("$iopadmap$%s.%s", module->name.unescaped(), wire->name.unescaped())}),
module->design->twines.add(Twine{RTLIL::escape_id(celltype)}));
cell->setPort(module->design->twines.add(Twine{RTLIL::escape_id(portname_int)}), RTLIL::SigSpec(wire));
if (!portname_pad.empty()) {
RTLIL::Wire *new_wire = NULL;
new_wire = module->addWire(
module->uniquify(stringf("$iopadmap$%s", wire)),
module->uniquify(Twine{stringf("$iopadmap$%s", wire)}),
wire);
module->swap_names(new_wire, wire);
wire->attributes.clear();
cell->setPort(RTLIL::escape_id(portname_pad), RTLIL::SigSpec(new_wire));
cell->setPort(module->design->twines.add(Twine{RTLIL::escape_id(portname_pad)}), RTLIL::SigSpec(new_wire));
}
if (!widthparam.empty())
cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width);
if (!nameparam.empty())
cell->parameters[RTLIL::escape_id(nameparam)] = design->twines.unescaped_str(RTLIL::Const(wire->name));
cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(wire->name.unescape());
cell->attributes[ID::keep] = RTLIL::Const(1);
}
@ -503,7 +503,7 @@ struct IopadmapPass : public Pass {
for (auto &it : rewrite_bits) {
RTLIL::Wire *wire = it.first;
RTLIL::Wire *new_wire = module->addWire(
module->uniquify(stringf("$iopadmap$%s", wire)),
module->uniquify(Twine{stringf("$iopadmap$%s", wire)}),
wire);
module->swap_names(new_wire, wire);
wire->attributes.clear();

38
passes/techmap/shregmap.cc
View file

@ -36,7 +36,7 @@ struct ShregmapOptions
int minlen, maxlen;
int keep_before, keep_after;
bool zinit, init, params, ffe;
dict<IdString, pair<IdString, IdString>> ffcells;
dict<TwineRef, pair<TwineRef, TwineRef>> ffcells;
ShregmapTech *tech;
ShregmapOptions()
@ -75,14 +75,14 @@ struct ShregmapTechGreenpak4 : ShregmapTech
auto D = cell->getPort(TW::D);
auto C = cell->getPort(TW::C);
auto newcell = cell->module->addCell(NEW_TWINE, ID(GP_SHREG));
auto newcell = cell->module->addCell(NEW_TWINE, TW::GP_SHREG);
newcell->setPort(TW::nRST, State::S1);
newcell->setPort(TW::CLK, C);
newcell->setPort(TW::IN, D);
int i = 0;
for (auto tap : taps) {
newcell->setPort(i ? ID(OUTB) : ID(OUTA), tap.second);
newcell->setPort(i ? TW::OUTB : TW::OUTA, tap.second);
newcell->setParam(i ? ID(OUTB_TAP) : ID(OUTA_TAP), tap.first + 1);
i++;
}
@ -120,10 +120,10 @@ struct ShregmapWorker
for (auto cell : module->cells())
{
if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute(ID::keep))
if (opts.ffcells.count(cell->type_impl) && !cell->get_bool_attribute(ID::keep))
{
IdString d_port = opts.ffcells.at(cell->type).first;
IdString q_port = opts.ffcells.at(cell->type).second;
TwineRef d_port = opts.ffcells.at(cell->type_impl).first;
TwineRef q_port = opts.ffcells.at(cell->type_impl).second;
SigBit d_bit = sigmap(cell->getPort(d_port).as_bit());
SigBit q_bit = sigmap(cell->getPort(q_port).as_bit());
@ -178,8 +178,8 @@ struct ShregmapWorker
if (c1->parameters != c2->parameters)
goto start_cell;
IdString d_port = opts.ffcells.at(c1->type).first;
IdString q_port = opts.ffcells.at(c1->type).second;
TwineRef d_port = opts.ffcells.at(c1->type_impl).first;
TwineRef q_port = opts.ffcells.at(c1->type_impl).second;
auto c1_conn = c1->connections();
auto c2_conn = c2->connections();
@ -210,7 +210,7 @@ struct ShregmapWorker
{
chain.push_back(c);
IdString q_port = opts.ffcells.at(c->type).second;
TwineRef q_port = opts.ffcells.at(c->type_impl).second;
SigBit q_bit = sigmap(c->getPort(q_port).as_bit());
if (sigbit_chain_next.count(q_bit) == 0)
@ -238,7 +238,7 @@ struct ShregmapWorker
depth = std::min(opts.maxlen, depth);
Cell *first_cell = chain[cursor];
IdString q_port = opts.ffcells.at(first_cell->type).second;
TwineRef q_port = opts.ffcells.at(first_cell->type_impl).second;
dict<int, SigBit> taps_dict;
if (opts.tech)
@ -456,9 +456,9 @@ struct ShregmapPass : public Pass {
match_args.push_back("D");
if (GetSize(match_args) < 3)
match_args.push_back("Q");
IdString id_cell_type(RTLIL::escape_id(match_args[0]));
IdString id_d_port_name(RTLIL::escape_id(match_args[1]));
IdString id_q_port_name(RTLIL::escape_id(match_args[2]));
TwineRef id_cell_type = design->twines.add(std::string{RTLIL::escape_id(match_args[0])});
TwineRef id_d_port_name = design->twines.add(std::string{RTLIL::escape_id(match_args[1])});
TwineRef id_q_port_name = design->twines.add(std::string{RTLIL::escape_id(match_args[2])});
opts.ffcells[id_cell_type] = make_pair(id_d_port_name, id_q_port_name);
continue;
}
@ -519,19 +519,19 @@ struct ShregmapPass : public Pass {
bool en_neg = enpol == "neg" || enpol == "any" || enpol == "any_or_none";
if (clk_pos && en_none)
opts.ffcells[TW($_DFF_P_)] = make_pair(IdString(ID::D), IdString(ID::Q));
opts.ffcells[TW($_DFF_P_)] = make_pair(TW::D, TW::Q);
if (clk_neg && en_none)
opts.ffcells[TW($_DFF_N_)] = make_pair(IdString(ID::D), IdString(ID::Q));
opts.ffcells[TW($_DFF_N_)] = make_pair(TW::D, TW::Q);
if (clk_pos && en_pos)
opts.ffcells[TW($_DFFE_PP_)] = make_pair(IdString(ID::D), IdString(ID::Q));
opts.ffcells[TW($_DFFE_PP_)] = make_pair(TW::D, TW::Q);
if (clk_pos && en_neg)
opts.ffcells[TW($_DFFE_PN_)] = make_pair(IdString(ID::D), IdString(ID::Q));
opts.ffcells[TW($_DFFE_PN_)] = make_pair(TW::D, TW::Q);
if (clk_neg && en_pos)
opts.ffcells[TW($_DFFE_NP_)] = make_pair(IdString(ID::D), IdString(ID::Q));
opts.ffcells[TW($_DFFE_NP_)] = make_pair(TW::D, TW::Q);
if (clk_neg && en_neg)
opts.ffcells[TW($_DFFE_NN_)] = make_pair(IdString(ID::D), IdString(ID::Q));
opts.ffcells[TW($_DFFE_NN_)] = make_pair(TW::D, TW::Q);
if (en_pos || en_neg)
opts.ffe = true;

65
passes/techmap/techmap.cc
View file

@ -54,7 +54,7 @@ void apply_prefix(IdString prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
if (chunk.wire != nullptr) {
IdString wire_name = chunk.wire->name;
apply_prefix(prefix, wire_name);
TwineRef wire_ref = module->design->twines.add(Twine{wire_name.str()});
TwineRef wire_ref = module->design->twines.add(std::string{wire_name.str()});
log_assert(module->wire(wire_ref) != nullptr);
chunk.wire = module->wire(wire_ref);
}
@ -120,7 +120,7 @@ struct TechmapWorker
return result;
for (auto w : module->wires()) {
if (*w->name.c_str() == '$')
if (w->name.str()[0] == '$')
continue;
if (w->name.contains("_TECHMAP_") && !w->name.contains("_TECHMAP_REPLACE_")) {
@ -168,7 +168,7 @@ struct TechmapWorker
orig_cell_name = cell->name.str();
for (auto tpl_cell : tpl->cells())
if (tpl_cell->name.ends_with("_TECHMAP_REPLACE_")) {
module->rename(cell, module->design->twines.add(Twine{stringf("$techmap%d", autoidx++) + cell->name.str()}));
module->rename(cell, module->design->twines.add(std::string{stringf("$techmap%d", autoidx++) + cell->name.str()}));
break;
}
@ -178,7 +178,7 @@ struct TechmapWorker
IdString old_m_id(std::string(tpl->design->twines.str(it.first)));
IdString m_name_id = old_m_id;
apply_prefix(cell->name, m_name_id);
TwineRef m_ref = module->design->twines.add(Twine{m_name_id.str()});
TwineRef m_ref = module->design->twines.add(std::string{m_name_id.str()});
RTLIL::Memory *m = module->addMemory(m_ref, it.second);
if (m->has_attribute(ID::src))
design->merge_src(m, src_cell);
@ -194,7 +194,7 @@ struct TechmapWorker
{
if (tpl_w->port_id > 0)
{
TwineRef posportref = module->design->twines.add(Twine{stringf("$%d", tpl_w->port_id)});
TwineRef posportref = module->design->twines.add(std::string{stringf("$%d", tpl_w->port_id)});
positional_ports.emplace(posportref, tpl_w->name.ref());
if (tpl_w->get_bool_attribute(ID::techmap_autopurge) &&
@ -211,7 +211,7 @@ struct TechmapWorker
}
IdString w_name = tpl_w->name;
apply_prefix(cell->name, w_name);
TwineRef w_ref = module->design->twines.add(Twine{w_name.str()});
TwineRef w_ref = module->design->twines.add(std::string{w_name.str()});
RTLIL::Wire *w = module->wire(w_ref);
if (w != nullptr) {
temp_renamed_wires[w] = w->name.ref();
@ -219,7 +219,7 @@ struct TechmapWorker
w = nullptr;
}
if (w == nullptr) {
w = module->addWire(Twine{w_name.str()}, tpl_w);
w = module->addWire(w_ref, tpl_w);
w->port_input = false;
w->port_output = false;
w->port_id = 0;
@ -231,8 +231,8 @@ struct TechmapWorker
}
design->select(module, w);
if (const char *p = strstr(tpl_w->name.c_str(), "_TECHMAP_REPLACE_.")) {
Wire *replace_w = module->addWire(Twine{std::string(orig_cell_name) + (p + strlen("_TECHMAP_REPLACE_"))}, tpl_w);
if (const char *p = strstr(tpl_w->name.str().c_str(), "_TECHMAP_REPLACE_.")) {
Wire *replace_w = module->addWire(module->design->twines.add(std::string{std::string(orig_cell_name) + (p + strlen("_TECHMAP_REPLACE_"))}), tpl_w);
module->connect(replace_w, w);
}
}
@ -335,16 +335,16 @@ struct TechmapWorker
if (techmap_replace_cell)
c_name = orig_cell_name;
else if (const char *p = strstr(tpl_cell->name.c_str(), "_TECHMAP_REPLACE_."))
else if (const char *p = strstr(tpl_cell->name.str().c_str(), "_TECHMAP_REPLACE_."))
c_name = stringf("%s%s", orig_cell_name, p + strlen("_TECHMAP_REPLACE_"));
else
apply_prefix(cell->name, c_name);
RTLIL::Cell *c = module->addCell(module->design->twines.add(Twine{c_name.str()}), tpl_cell);
RTLIL::Cell *c = module->addCell(module->design->twines.add(std::string{c_name.str()}), tpl_cell);
design->select(module, c);
if (c->type.in(TwineRef{TW(_TECHMAP_PLACEHOLDER_)}) && tpl_cell->has_attribute(ID::techmap_chtype)) {
c->type_impl = module->design->twines.add(Twine{RTLIL::escape_id(tpl_cell->get_string_attribute(ID::techmap_chtype))});
c->type_impl = module->design->twines.add(std::string{RTLIL::escape_id(tpl_cell->get_string_attribute(ID::techmap_chtype))});
c->attributes.erase(ID::techmap_chtype);
}
@ -457,7 +457,7 @@ struct TechmapWorker
continue;
for (auto &tpl_name : celltypeMap.at(cell->type)) {
RTLIL::Module *tpl = map->module(tpl_name);
RTLIL::Module *tpl = map->module(map->twines.add(std::string{tpl_name.str()}));
RTLIL::Wire *port = tpl->wire(conn.first);
if (port && port->port_input)
cell_to_inbit[cell].insert(sig.begin(), sig.end());
@ -485,8 +485,8 @@ struct TechmapWorker
for (auto &tpl_name : celltypeMap.at(cell->type))
{
TwineRef derived_name = map->twines.add(Twine{tpl_name.str()});
RTLIL::Module *tpl = map->module(tpl_name);
TwineRef derived_name = map->twines.add(std::string{tpl_name.str()});
RTLIL::Module *tpl = map->module(derived_name);
dict<IdString, RTLIL::Const> parameters(cell->parameters);
if (tpl->get_blackbox_attribute(ignore_wb))
@ -516,11 +516,11 @@ struct TechmapWorker
m_name += ":" + sha1(tpl->attributes.at(ID::techmap_wrap).decode_string());
RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design;
RTLIL::Module *extmapper_module = extmapper_design->module(IdString(m_name));
RTLIL::Module *extmapper_module = extmapper_design->module(extmapper_design->twines.add(std::string{m_name}));
if (extmapper_module == nullptr)
{
extmapper_module = extmapper_design->addModule(extmapper_design->twines.add(Twine{m_name}));
extmapper_module = extmapper_design->addModule(extmapper_design->twines.add(std::string{m_name}));
RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type.ref(), cell);
// addCell(name, cell) already migrated src across
// designs via copy_src_into — no need for an
@ -710,7 +710,7 @@ struct TechmapWorker
}
}
RTLIL::Module *constmapped_tpl = map->module(constmap_tpl_name(sigmap, tpl, cell, false));
RTLIL::Module *constmapped_tpl = map->module(map->twines.add(std::string{constmap_tpl_name(sigmap, tpl, cell, false)}));
if (constmapped_tpl != nullptr)
tpl = constmapped_tpl;
@ -757,10 +757,9 @@ struct TechmapWorker
techmap_wire_names.erase(it.first);
std::string final_id = data.wire->name.unescaped();
size_t start_idx = final_id.empty() ? 0 : 1;
size_t dot_pos = final_id.rfind('.', start_idx);
size_t split_idx = (dot_pos != std::string::npos) ? (dot_pos + 1) : start_idx;
std::string final_id = data.wire->name.escaped();
size_t last_dot = final_id.find_last_of('.');
size_t split_idx = (last_dot != std::string::npos) ? (last_dot + 1) : 1;
std::string cmd_string = data.value.as_const().decode_string();
@ -772,9 +771,9 @@ struct TechmapWorker
log("Analyzing pattern of constant bits for this cell:\n");
IdString new_tpl_name = constmap_tpl_name(sigmap, tpl, cell, true);
log("Creating constmapped module `%s'.\n", log_id(new_tpl_name));
log_assert(map->module(new_tpl_name) == nullptr);
log_assert(map->module(map->twines.add(std::string{new_tpl_name.str()})) == nullptr);
RTLIL::Module *new_tpl = map->addModule(map->twines.add(Twine{new_tpl_name.str()}));
RTLIL::Module *new_tpl = map->addModule(map->twines.add(std::string{new_tpl_name.str()}));
tpl->cloneInto(new_tpl);
techmap_do_cache.erase(tpl);
@ -793,7 +792,7 @@ struct TechmapWorker
IdString port_name = wire->name;
tpl->rename(wire, tpl->design->twines.add(NEW_TWINE));
RTLIL::Wire *new_wire = tpl->addWire(Twine{port_name.str()}, wire);
RTLIL::Wire *new_wire = tpl->addWire(tpl->design->twines.add(std::string{port_name.str()}), wire);
wire->port_input = false;
wire->port_id = 0;
@ -865,13 +864,13 @@ struct TechmapWorker
Pass::call_on_module(map, tpl, cmd_string);
map->sigNormalize(false);
// log_assert(!strncmp(q, "_TECHMAP_DO_", 12));
log_assert(final_id.compare(split_idx, 12, "_TECHMAP_DO_") == 0);
std::string new_name = final_id.substr(0, split_idx)
+ "_TECHMAP_DONE_"
+ final_id.substr(split_idx + 12);
while (tpl->wire(tpl->design->twines.add(Twine{new_name})) != nullptr)
while (tpl->wire(tpl->design->twines.add(std::string{new_name})) != nullptr)
new_name += "_";
tpl->rename(data.wire->name.ref(), tpl->design->twines.add(Twine{new_name}));
tpl->rename(data.wire->name.ref(), tpl->design->twines.add(std::string{new_name}));
keep_running = true;
break;
@ -917,7 +916,7 @@ struct TechmapWorker
for (auto &it2 : it.second) {
auto val = it2.value.as_const();
auto wirename = RTLIL::escape_id(it.first.substr(21, it.first.size() - 21 - 1));
TwineRef wirename_ref = cell->module->design->twines.add(Twine{wirename});
TwineRef wirename_ref = cell->module->design->twines.add(std::string{wirename});
auto it = cell->connections().find(wirename_ref);
if (it != cell->connections().end()) {
auto sig = sigmap(it->second);
@ -933,16 +932,16 @@ struct TechmapWorker
{
std::string m_name = stringf("$extern:%s", log_id(tpl->name));
if (!design->module(RTLIL::IdString(m_name)))
if (!design->module(design->twines.add(std::string{m_name})))
{
RTLIL::Module *m = design->addModule(design->twines.add(Twine{m_name}));
RTLIL::Module *m = design->addModule(design->twines.add(std::string{m_name}));
tpl->cloneInto(m);
module_queue.insert(m);
}
log_debug("%s %s.%s to imported %s.\n", mapmsg_prefix.c_str(), log_id(module->name), log_id(cell->name), m_name.c_str());
cell->type_impl = cell->module->design->twines.add(Twine{m_name});
cell->type_impl = cell->module->design->twines.add(std::string{m_name});
cell->parameters.clear();
}
else
@ -1233,7 +1232,7 @@ struct TechmapPass : public Pass {
log_cmd_error("Can't open saved design `%s'.\n", fn.c_str()+1);
}
for (auto mod : saved_designs.at(fn.substr(1))->modules())
if (!map->module(IdString(mod->name)))
if (!map->module(map->twines.add(std::string{mod->name.str()})))
mod->clone(map);
} else {
Frontend::frontend_call(map, nullptr, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : verilog_frontend));

48
passes/tests/test_cell.cc
View file

@ -39,10 +39,10 @@ static uint32_t xorshift32(uint32_t limit) {
return xorshift32_state % limit;
}
static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, std::string cell_type_flags, bool constmode, bool muxdiv)
static RTLIL::Cell* create_gold_module(RTLIL::Design *design, TwineRef cell_type, std::string cell_type_flags, bool constmode, bool muxdiv)
{
RTLIL::Module *module = design->addModule(design->twines.add(Twine{ID(gold).str()}));
RTLIL::Cell *cell = module->addCell(design->twines.add(Twine{ID(UUT).str()}), cell_type);
RTLIL::Module *module = design->addModule(TW::gold);
RTLIL::Cell *cell = module->addCell(TW::UUT, cell_type);
RTLIL::Wire *wire;
if (cell_type.in(TW($mux), TW($pmux)))
@ -573,8 +573,8 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
{
log("Eval testing:%c", verbose ? '\n' : ' ');
RTLIL::Module *gold_mod = design->module(ID(gold));
RTLIL::Module *gate_mod = design->module(ID(gate));
RTLIL::Module *gold_mod = design->module(TW::gold);
RTLIL::Module *gate_mod = design->module(TW::gate);
ConstEval gold_ce(gold_mod), gate_ce(gate_mod);
ezSatPtr ez1, ez2;
@ -981,8 +981,8 @@ struct TestCellPass : public Pass {
log("Rng seed value: %d\n", int(xorshift32_state));
}
std::map<IdString, std::string> cell_types;
std::vector<IdString> selected_cell_types;
std::map<TwineRef, std::string> cell_types;
std::vector<TwineRef> selected_cell_types;
cell_types[TW($not)] = "ASY";
cell_types[TW($pos)] = "ASY";
@ -1080,6 +1080,13 @@ struct TestCellPass : public Pass {
cell_types[TW($_AOI4_)] = "ABCDYb";
cell_types[TW($_OAI4_)] = "ABCDYb";
auto find_type = [&](const std::string &s) -> TwineRef {
for (auto &it : cell_types)
if (TW::str(it.first) == s)
return it.first;
return Twine::Null;
};
for (; argidx < GetSize(args); argidx++)
{
if (args[argidx].rfind("-", 0) == 0)
@ -1093,37 +1100,38 @@ struct TestCellPass : public Pass {
}
if (args[argidx].compare(0, 1, "/") == 0) {
std::vector<IdString> new_selected_cell_types;
std::vector<TwineRef> new_selected_cell_types;
for (auto it : selected_cell_types)
if (it != args[argidx].substr(1))
if (TW::str(it) != args[argidx].substr(1))
new_selected_cell_types.push_back(it);
new_selected_cell_types.swap(selected_cell_types);
continue;
}
if (cell_types.count(args[argidx]) == 0) {
TwineRef arg_type = find_type(args[argidx]);
if (arg_type == Twine::Null) {
std::string cell_type_list;
int charcount = 100;
for (auto &it : cell_types) {
if (charcount > 60) {
cell_type_list += stringf("\n%s", design->twines.unescaped_str(it.first));
cell_type_list += stringf("\n%s", TW::str(it.first).c_str());
charcount = 0;
} else
cell_type_list += stringf(" %s", design->twines.unescaped_str(it.first));
charcount += GetSize(it.first);
cell_type_list += stringf(" %s", TW::str(it.first).c_str());
charcount += GetSize(TW::str(it.first));
}
log_cmd_error("The cell type `%s' is currently not supported. Try one of these:%s\n",
args[argidx].c_str(), cell_type_list.c_str());
}
if (std::count(selected_cell_types.begin(), selected_cell_types.end(), args[argidx]) == 0)
selected_cell_types.push_back(args[argidx]);
if (std::count(selected_cell_types.begin(), selected_cell_types.end(), arg_type) == 0)
selected_cell_types.push_back(arg_type);
}
if (!rtlil_file.empty()) {
if (!selected_cell_types.empty())
log_cmd_error("Do not specify any cell types when using -f.\n");
selected_cell_types.push_back(ID(rtlil));
selected_cell_types.push_back(TW(rtlil));
}
if (selected_cell_types.empty())
@ -1161,7 +1169,7 @@ struct TestCellPass : public Pass {
}
if (is_unconverted) {
// skip unconverted cells
log_warning("Skipping %s\n", cell_type);
log_warning("Skipping %s\n", TW::str(cell_type).c_str());
delete design;
break;
} else {
@ -1169,7 +1177,7 @@ struct TestCellPass : public Pass {
suffix = "aag";
}
}
Pass::call(design, stringf("%s %s_%s_%05d.%s", writer, write_prefix, cell_type.c_str()+1, i, suffix));
Pass::call(design, stringf("%s %s_%s_%05d.%s", writer, write_prefix, TW::str(cell_type).c_str()+1, i, suffix));
} else if (edges) {
Pass::call(design, "dump gold");
run_edges_test(design, verbose);
@ -1184,7 +1192,7 @@ struct TestCellPass : public Pass {
Pass::call(design, "dump gold");
if (!nosat)
Pass::call(design, "sat -verify -enable_undef -prove trigger 0 -show-inputs -show-outputs miter");
std::string uut_name = stringf("uut_%s_%d", cell_type.substr(1), i);
std::string uut_name = stringf("uut_%s_%d", TW::str(cell_type).substr(1), i);
if (vlog_file.is_open()) {
Pass::call(design, stringf("copy gold %s_expr; select %s_expr", uut_name, uut_name));
Backend::backend_call(design, &vlog_file, "<test_cell -vlog>", "verilog -selected");
@ -1228,7 +1236,7 @@ struct TestCellPass : public Pass {
if (check_cost && failed) {
log_warning("Cell type %s cost underestimated in %.1f%% cases "
"with worst offender being by %d (%.1f%%)\n",
cell_type.c_str(), 100 * (float)failed / (float)num_iter,
TW::str(cell_type).c_str(), 100 * (float)failed / (float)num_iter,
worst_abs, 100 * worst_rel);
}
}

2
techlibs/anlogic/anlogic_fixcarry.cc
View file

@ -79,7 +79,7 @@ static void fix_carry_chain(Module *module)
SigBit canonical_bit = sigmap(bit_ci);
auto bit = mapping_bits.at(canonical_bit);
log("Fixing %s cell named %s breaking carry chain.\n", cell->type.unescaped(), cell);
Cell *c = module->addCell(NEW_TWINE, ID(AL_MAP_ADDER));
Cell *c = module->addCell(NEW_TWINE, module->design->twines.add(std::string{"\\AL_MAP_ADDER"}));
SigBit new_bit = module->addWire(NEW_TWINE);
SigBit dummy_bit = module->addWire(NEW_TWINE);
SigSpec bits;

2
techlibs/efinix/efinix_fixcarry.cc
View file

@ -75,7 +75,7 @@ static void fix_carry_chain(Module *module)
SigBit canonical_bit = sigmap(bit_ci);
auto bit = mapping_bits.at(canonical_bit);
log("Fixing %s cell named %s breaking carry chain.\n", cell->type.unescaped(), cell);
Cell *c = module->addCell(NEW_TWINE, ID(EFX_ADD));
Cell *c = module->addCell(NEW_TWINE, module->design->twines.add(std::string{"\\EFX_ADD"}));
SigBit new_bit = module->addWire(NEW_TWINE);
c->setParam(ID(I0_POLARITY), State::S1);
c->setParam(ID(I1_POLARITY), State::S1);

26
techlibs/gatemate/gatemate_foldinv.cc
View file

@ -30,7 +30,7 @@ struct LUTPin {
};
struct LUTType {
dict<IdString, LUTPin> inputs;
dict<TwineRef, LUTPin> inputs;
IdString output_param;
};
@ -46,21 +46,21 @@ struct FoldInvWorker {
const dict<IdString, LUTType> lut_types = {
{ID(CC_LUT2), {{
{ID(I0), {0, ID(INIT)}},
{ID(I1), {1, ID(INIT)}},
{TW::I0, {0, ID(INIT)}},
{TW::I1, {1, ID(INIT)}},
}, ID(INIT)}},
{ID(CC_L2T4), {{
{ID(I0), {0, ID(INIT_L00)}},
{ID(I1), {1, ID(INIT_L00)}},
{ID(I2), {0, ID(INIT_L01)}},
{ID(I3), {1, ID(INIT_L01)}},
{TW::I0, {0, ID(INIT_L00)}},
{TW::I1, {1, ID(INIT_L00)}},
{TW::I2, {0, ID(INIT_L01)}},
{TW::I3, {1, ID(INIT_L01)}},
}, ID(INIT_L10)}},
{ID(CC_L2T5), {{
{ID(I0), {0, ID(INIT_L02)}},
{ID(I1), {1, ID(INIT_L02)}},
{ID(I2), {0, ID(INIT_L03)}},
{ID(I3), {1, ID(INIT_L03)}},
{ID(I4), {0, ID(INIT_L20)}},
{TW::I0, {0, ID(INIT_L02)}},
{TW::I1, {1, ID(INIT_L02)}},
{TW::I2, {0, ID(INIT_L03)}},
{TW::I3, {1, ID(INIT_L03)}},
{TW::I4, {0, ID(INIT_L20)}},
}, ID(INIT_L20)}},
};
@ -162,7 +162,7 @@ struct FoldInvWorker {
continue;
// Create a duplicate of the LUT with an inverted output
// (if the uninverted version becomes unused it will be swept away)
Cell *dup_lut = module->addCell(NEW_TWINE, orig_lut->type);
Cell *dup_lut = module->addCell(NEW_TWINE, orig_lut->type_impl);
inv->unsetPort(TW::Y);
dup_lut->setPort(TW::O, inv_y);
for (auto conn : orig_lut->connections()) {

4
techlibs/greenpak4/greenpak4_dffinv.cc
View file

@ -81,9 +81,9 @@ void invert_gp_dff(Cell *cell, bool invert_input)
}
if(cell_type_latch)
cell->type = stringf("\\GP_DLATCH%s%s%s", cell_type_s ? "S" : "", cell_type_r ? "R" : "", cell_type_i ? "I" : "");
cell->type_impl = cell->module->design->twines.add(std::string{stringf("\\GP_DLATCH%s%s%s", cell_type_s ? "S" : "", cell_type_r ? "R" : "", cell_type_i ? "I" : "")});
else
cell->type = stringf("\\GP_DFF%s%s%s", cell_type_s ? "S" : "", cell_type_r ? "R" : "", cell_type_i ? "I" : "");
cell->type_impl = cell->module->design->twines.add(std::string{stringf("\\GP_DFF%s%s%s", cell_type_s ? "S" : "", cell_type_r ? "R" : "", cell_type_i ? "I" : "")});
log("Merged %s inverter into cell %s.%s: %s -> %s\n", invert_input ? "input" : "output",
cell->module, cell, cell_type.c_str()+1, cell->type.unescaped());

30
techlibs/ice40/ice40_dsp.cc
View file

@ -31,15 +31,15 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
log("Checking %s.%s for iCE40 DSP inference.\n", pm.module, st.mul);
log_debug("ffA: %s\n", st.ffA ? design->twines.unescaped_str(st.ffA->name) : "--");
log_debug("ffB: %s\n", st.ffB ? design->twines.unescaped_str(st.ffB->name) : "--");
log_debug("ffCD: %s\n", st.ffCD ? design->twines.unescaped_str(st.ffCD->name) : "--");
log_debug("mul: %s\n", st.mul ? design->twines.unescaped_str(st.mul->name) : "--");
log_debug("ffFJKG: %s\n", st.ffFJKG ? design->twines.unescaped_str(st.ffFJKG->name) : "--");
log_debug("ffH: %s\n", st.ffH ? design->twines.unescaped_str(st.ffH->name) : "--");
log_debug("add: %s\n", st.add ? design->twines.unescaped_str(st.add->name) : "--");
log_debug("mux: %s\n", st.mux ? design->twines.unescaped_str(st.mux->name) : "--");
log_debug("ffO: %s\n", st.ffO ? design->twines.unescaped_str(st.ffO->name) : "--");
log_debug("ffA: %s\n", st.ffA ? pm.module->design->twines.unescaped_str(st.ffA->name.ref()) : "--");
log_debug("ffB: %s\n", st.ffB ? pm.module->design->twines.unescaped_str(st.ffB->name.ref()) : "--");
log_debug("ffCD: %s\n", st.ffCD ? pm.module->design->twines.unescaped_str(st.ffCD->name.ref()) : "--");
log_debug("mul: %s\n", st.mul ? pm.module->design->twines.unescaped_str(st.mul->name.ref()) : "--");
log_debug("ffFJKG: %s\n", st.ffFJKG ? pm.module->design->twines.unescaped_str(st.ffFJKG->name.ref()) : "--");
log_debug("ffH: %s\n", st.ffH ? pm.module->design->twines.unescaped_str(st.ffH->name.ref()) : "--");
log_debug("add: %s\n", st.add ? pm.module->design->twines.unescaped_str(st.add->name.ref()) : "--");
log_debug("mux: %s\n", st.mux ? pm.module->design->twines.unescaped_str(st.mux->name.ref()) : "--");
log_debug("ffO: %s\n", st.ffO ? pm.module->design->twines.unescaped_str(st.ffO->name.ref()) : "--");
log_debug("\n");
if (GetSize(st.sigA) > 16) {
@ -64,9 +64,9 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
Cell *cell = st.mul;
if (cell->type == TW($mul)) {
log(" replacing %s with SB_MAC16 cell.\n", design->twines.unescaped_str(st.mul->type));
log(" replacing %s with SB_MAC16 cell.\n", pm.module->design->twines.unescaped_str(st.mul->type_impl));
cell = pm.module->addCell(NEW_TWINE, ID(SB_MAC16));
cell = pm.module->addCell(NEW_TWINE, TW::SB_MAC16);
pm.module->swap_names(cell, st.mul);
}
else log_assert(cell->type == ID(SB_MAC16));
@ -194,11 +194,11 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
bool accum = false;
if (st.add) {
accum = (st.ffO && st.add->getPort(st.addAB == ID::A ? ID::B : ID::A) == st.sigO);
accum = (st.ffO && st.add->getPort(st.addAB == TW::A ? TW::B : TW::A) == st.sigO);
if (accum)
log(" accumulator %s (%s)\n", st.add, design->twines.unescaped_str(st.add->type));
log(" accumulator %s (%s)\n", st.add, pm.module->design->twines.unescaped_str(st.add->type_impl));
else
log(" adder %s (%s)\n", st.add, design->twines.unescaped_str(st.add->type));
log(" adder %s (%s)\n", st.add, pm.module->design->twines.unescaped_str(st.add->type_impl));
cell->setPort(TW::ADDSUBTOP, st.add->type == TW($add) ? State::S0 : State::S1);
cell->setPort(TW::ADDSUBBOT, st.add->type == TW($add) ? State::S0 : State::S1);
} else {
@ -259,7 +259,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
else
cell->setParam(ID(TOPOUTPUT_SELECT), Const(1, 2));
st.ffO->connections_.at(ID::Q).replace(O, pm.module->addWire(NEW_TWINE, GetSize(O)));
st.ffO->connections_.at(TW::Q).replace(O, pm.module->addWire(NEW_TWINE, GetSize(O)));
cell->setParam(ID(BOTOUTPUT_SELECT), Const(1, 2));
}
else {

10
techlibs/ice40/ice40_dsp.pmg
View file

@ -4,7 +4,7 @@ state <SigBit> clock
state <bool> clock_pol cd_signed o_lo
state <SigSpec> sigA sigB sigCD sigH sigO
state <Cell*> add mux
state <IdString> addAB muxAB
state <TwineRef> addAB muxAB
state <Cell*> ffA ffB ffCD
state <Cell*> ffFJKG ffH ffO
@ -337,9 +337,9 @@ code
for (auto c : argQ.chunks()) {
if (!c.wire)
reject;
if (c.wire->get_bool_attribute(\keep))
if (c.wire->get_bool_attribute(ID(keep)))
reject;
Const init = c.wire->attributes.at(\init, State::Sx);
Const init = c.wire->attributes.at(ID(init), State::Sx);
if (!init.is_fully_undef() && !init.is_fully_zero())
reject;
}
@ -386,7 +386,7 @@ arg argD argSdff argQ clock clock_pol
code
dff = nullptr;
for (auto c : argD.chunks())
if (c.wire->get_bool_attribute(\keep))
if (c.wire->get_bool_attribute(ID(keep)))
reject;
endcode
@ -419,7 +419,7 @@ code argQ
argQ.replace(D, Q);
for (auto c : argQ.chunks()) {
Const init = c.wire->attributes.at(\init, State::Sx);
Const init = c.wire->attributes.at(ID(init), State::Sx);
if (!init.is_fully_undef() && !init.is_fully_zero())
reject;
}

8
techlibs/ice40/ice40_opt.cc
View file

@ -119,7 +119,7 @@ static void run_ice40_opts(Module *module)
optimized_co.insert(sigmap(cell->getPort(TW::CO)[0]));
auto it = cell->attributes.find(IdString{"\\SB_LUT4.name"});
if (it != cell->attributes.end()) {
module->rename(cell, it->second.decode_string());
module->rename(cell, module->design->twines.add(std::string{it->second.decode_string()}));
decltype(Cell::attributes) new_attr;
for (const auto &a : cell->attributes)
if (a.first.begins_with("\\SB_LUT4.\\"))
@ -138,8 +138,8 @@ static void run_ice40_opts(Module *module)
module->design->scratchpad_set_bool("opt.did_something", true);
log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
module, cell, log_signal(replacement_output));
cell->type = TW($lut);
auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID::CI : ID(I3)));
cell->type_impl = TW($lut);
auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? TW::CI : TW::I3));
cell->setPort(TW::A, { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort(TW::I0)) });
cell->setPort(TW::Y, cell->getPort(TW::O));
cell->unsetPort(TW::B);
@ -177,7 +177,7 @@ static void run_ice40_opts(Module *module)
module->design->scratchpad_set_bool("opt.did_something", true);
log("Mapping SB_LUT4 cell %s.%s back to logic.\n", module, cell);
cell->type = TW($lut);
cell->type_impl = TW($lut);
cell->setParam(ID::WIDTH, 4);
cell->setParam(ID::LUT, cell->getParam(ID(LUT_INIT)));
cell->unsetParam(ID(LUT_INIT));

10
techlibs/ice40/ice40_wrapcarry.cc
View file

@ -134,17 +134,17 @@ struct Ice40WrapCarryPass : public Pass {
if (cell->type != TW($__ICE40_CARRY_WRAPPER))
continue;
auto carry = module->addCell(NEW_TWINE, ID(SB_CARRY));
auto carry = module->addCell(NEW_TWINE, TW::SB_CARRY);
carry->setPort(TW::I0, cell->getPort(TW::A));
carry->setPort(TW::I1, cell->getPort(TW::B));
carry->setPort(TW::CI, cell->getPort(TW::CI));
carry->setPort(TW::CO, cell->getPort(TW::CO));
module->swap_names(carry, cell);
auto lut_name = cell->attributes.at(IdString{"\\SB_LUT4.name"}, Const(NEW_ID.str())).decode_string();
auto lut = module->addCell(lut_name, TW($lut));
auto lut = module->addCell(module->design->twines.add(std::string{lut_name}), TW($lut));
lut->setParam(ID::WIDTH, 4);
lut->setParam(ID::LUT, cell->getParam(ID::LUT));
auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID::CI : ID(I3));
auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? TW::CI : TW::I3);
lut->setPort(TW::A, { I3, cell->getPort(TW::B), cell->getPort(TW::A), cell->getPort(TW::I0) });
lut->setPort(TW::Y, cell->getPort(TW::O));
@ -170,8 +170,8 @@ struct Ice40WrapCarryPass : public Pass {
}
if (carry_src.empty()) carry_src = fallback_src;
if (lut_src.empty()) lut_src = fallback_src;
if (!carry_src.empty()) carry->set_src_attribute(carry_src);
if (!lut_src.empty()) lut->set_src_attribute(lut_src);
if (!carry_src.empty()) carry->set_src_attribute(module->design->twines.add(Twine{carry_src}));
if (!lut_src.empty()) lut->set_src_attribute(module->design->twines.add(Twine{lut_src}));
module->remove(cell);
}

8
techlibs/microchip/microchip_dffopt.cc
View file

@ -309,16 +309,16 @@ struct MicrochipDffOptPass : public Pass {
Cell *lut_cell = nullptr;
switch (GetSize(final_lut.second)) {
case 1:
lut_cell = module->addCell(NEW_TWINE, ID(CFG1));
lut_cell = module->addCell(NEW_TWINE, TW::CFG1);
break;
case 2:
lut_cell = module->addCell(NEW_TWINE, ID(CFG2));
lut_cell = module->addCell(NEW_TWINE, TW::CFG2);
break;
case 3:
lut_cell = module->addCell(NEW_TWINE, ID(CFG3));
lut_cell = module->addCell(NEW_TWINE, TW::CFG3);
break;
case 4:
lut_cell = module->addCell(NEW_TWINE, ID(CFG4));
lut_cell = module->addCell(NEW_TWINE, TW::CFG4);
break;
default:
log_assert(!"unknown lut size");

34
techlibs/microchip/microchip_dsp.cc
View file

@ -36,8 +36,8 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
Cell *cell = st.dsp;
// pack pre-adder
if (st.preAdderStatic) {
SigSpec &pasub = cell->connections_.at(ID(PASUB));
log(" static PASUB preadder %s (%s)\n", st.preAdderStatic, design->twines.unescaped_str(st.preAdderStatic->type));
SigSpec &pasub = cell->connections_.at(TW::PASUB);
log(" static PASUB preadder %s (%s)\n", st.preAdderStatic, pm.module->design->twines.unescaped_str(st.preAdderStatic->type_impl));
bool D_SIGNED = st.preAdderStatic->getParam(ID::B_SIGNED).as_bool();
bool B_SIGNED = st.preAdderStatic->getParam(ID::A_SIGNED).as_bool();
st.sigB.extend_u0(18, B_SIGNED);
@ -60,8 +60,8 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
}
// pack post-adder
if (st.postAdderStatic) {
log(" postadder %s (%s)\n", st.postAdderStatic, design->twines.unescaped_str(st.postAdderStatic->type));
SigSpec &sub = cell->connections_.at(ID(SUB));
log(" postadder %s (%s)\n", st.postAdderStatic, pm.module->design->twines.unescaped_str(st.postAdderStatic->type_impl));
SigSpec &sub = cell->connections_.at(TW::SUB);
// Post-adder in MACC_PA also supports subtraction
// Determines the sign of the output from the multiplier.
if (st.postAdderStatic->type == TW($add))
@ -86,14 +86,14 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
cell->setPort(TW::CLK, st.clock);
// function to absorb a register
auto f = [&pm, cell](SigSpec &A, Cell *ff, IdString ceport, IdString rstport, IdString bypass) {
auto f = [&pm, cell](SigSpec &A, Cell *ff, TwineRef ceport, TwineRef rstport, TwineRef bypass) {
// input/output ports
SigSpec D = ff->getPort(TW::D);
SigSpec Q = (*pm.sigmap)(ff->getPort(TW::Q));
if (!A.empty())
A.replace(Q, D);
if (rstport != IdString()) {
if (rstport != Twine::Null) {
if (ff->type.in(TW($sdff), TW($sdffe))) {
SigSpec srst = ff->getPort(TW::SRST);
bool rstpol_n = !ff->getParam(ID::SRST_POLARITY).as_bool();
@ -138,7 +138,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
if (st.ffA) {
SigSpec A = cell->getPort(TW::A);
if (st.ffA) {
f(A, st.ffA, ID(A_EN), ID(A_SRST_N), ID(A_BYPASS));
f(A, st.ffA, TW::A_EN, TW::A_SRST_N, TW::A_BYPASS);
}
pm.add_siguser(A, cell);
cell->setPort(TW::A, A);
@ -146,7 +146,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
if (st.ffB) {
SigSpec B = cell->getPort(TW::B);
if (st.ffB) {
f(B, st.ffB, ID(B_EN), ID(B_SRST_N), ID(B_BYPASS));
f(B, st.ffB, TW::B_EN, TW::B_SRST_N, TW::B_BYPASS);
}
pm.add_siguser(B, cell);
cell->setPort(TW::B, B);
@ -154,9 +154,9 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
if (st.ffD) {
SigSpec D = cell->getPort(TW::D);
if (st.ffD->type.in(TW($adff), TW($adffe))) {
f(D, st.ffD, ID(D_EN), ID(D_ARST_N), ID(D_BYPASS));
f(D, st.ffD, TW::D_EN, TW::D_ARST_N, TW::D_BYPASS);
} else {
f(D, st.ffD, ID(D_EN), ID(D_SRST_N), ID(D_BYPASS));
f(D, st.ffD, TW::D_EN, TW::D_SRST_N, TW::D_BYPASS);
}
pm.add_siguser(D, cell);
@ -164,8 +164,8 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
}
if (st.ffP) {
SigSpec P; // unused
f(P, st.ffP, ID(P_EN), ID(P_SRST_N), ID(P_BYPASS));
st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_TWINE, GetSize(st.sigP)));
f(P, st.ffP, TW::P_EN, TW::P_SRST_N, TW::P_BYPASS);
st.ffP->connections_.at(TW::Q).replace(st.sigP, pm.module->addWire(NEW_TWINE, GetSize(st.sigP)));
}
log(" clock: %s (%s)\n", log_signal(st.clock), "posedge");
@ -195,7 +195,7 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
auto &st = pm.st_microchip_dsp_packC;
log_debug("Analysing %s.%s for Microchip DSP packing (REG_C).\n", pm.module, st.dsp);
log_debug("ffC: %s\n", st.ffC ? design->twines.unescaped_str(st.ffC->name) : "--");
log_debug("ffC: %s\n", st.ffC ? pm.module->design->twines.unescaped_str(st.ffC->name.ref()) : "--");
Cell *cell = st.dsp;
@ -203,13 +203,13 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
cell->setPort(TW::CLK, st.clock);
// same function as above, used for the last CREG we need to absorb
auto f = [&pm, cell](SigSpec &A, Cell *ff, IdString ceport, IdString rstport, IdString bypass) {
auto f = [&pm, cell](SigSpec &A, Cell *ff, TwineRef ceport, TwineRef rstport, TwineRef bypass) {
// input/output ports
SigSpec D = ff->getPort(TW::D);
SigSpec Q = (*pm.sigmap)(ff->getPort(TW::Q));
if (!A.empty())
A.replace(Q, D);
if (rstport != IdString()) {
if (rstport != Twine::Null) {
if (ff->type.in(TW($sdff), TW($sdffe))) {
SigSpec srst = ff->getPort(TW::SRST);
bool rstpol_n = !ff->getParam(ID::SRST_POLARITY).as_bool();
@ -253,9 +253,9 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
SigSpec C = cell->getPort(TW::C);
if (st.ffC->type.in(TW($adff), TW($adffe))) {
f(C, st.ffC, ID(C_EN), ID(C_ARST_N), ID(C_BYPASS));
f(C, st.ffC, TW::C_EN, TW::C_ARST_N, TW::C_BYPASS);
} else {
f(C, st.ffC, ID(C_EN), ID(C_SRST_N), ID(C_BYPASS));
f(C, st.ffC, TW::C_EN, TW::C_SRST_N, TW::C_BYPASS);
}
pm.add_siguser(C, cell);
cell->setPort(TW::C, C);

12
techlibs/microchip/microchip_dsp.pmg
View file

@ -50,8 +50,8 @@ udata <SigSpec> dffD dffQ
udata <SigBit> dffclock
udata <Cell*> dff
udata <Cell*> u_preAdderStatic u_postAdderStatic
udata <IdString> u_postAddAB
state <IdString> postAddAB
udata <TwineRef> u_postAddAB
state <TwineRef> postAddAB
// (1) Starting from a DSP cell
match dsp
@ -338,10 +338,10 @@ code
if (!c.wire)
reject;
// Abandon matches when 'Q' has the keep attribute set
if (c.wire->get_bool_attribute(\keep))
if (c.wire->get_bool_attribute(ID(keep)))
reject;
// Abandon matches when 'Q' has a non-zero init attribute set
Const init = c.wire->attributes.at(\init, Const());
Const init = c.wire->attributes.at(ID(init), Const());
if (!init.empty())
for (auto b : init.extract(c.offset, c.width))
if (b != State::Sx && b != State::S0)
@ -399,7 +399,7 @@ code
dff = nullptr;
for (auto c : argD.chunks())
// Abandon matches when 'D' has the keep attribute set
if (c.wire->get_bool_attribute(\keep))
if (c.wire->get_bool_attribute(ID(keep)))
reject;
endcode
@ -426,7 +426,7 @@ code argQ
// Abandon matches when 'Q' has a non-zero init attribute set
for (auto c : argQ.chunks()) {
Const init = c.wire->attributes.at(\init, Const());
Const init = c.wire->attributes.at(ID(init), Const());
if (!init.empty())
for (auto b : init.extract(c.offset, c.width))
if (b != State::Sx && b != State::S0)

4
techlibs/microchip/microchip_dsp_CREG.pmg
View file

@ -122,10 +122,10 @@ code
if (!c.wire)
reject;
// Abandon matches when 'Q' has the keep attribute set
if (c.wire->get_bool_attribute(\keep))
if (c.wire->get_bool_attribute(ID(keep)))
reject;
// Abandon matches when 'Q' has a non-zero init attribute set
Const init = c.wire->attributes.at(\init, Const());
Const init = c.wire->attributes.at(ID(init), Const());
if (!init.empty())
for (auto b : init.extract(c.offset, c.width))
if (b != State::Sx && b != State::S0)

12
techlibs/nanoxplore/nx_carry.cc
View file

@ -77,11 +77,11 @@ static void nx_carry_chain(Module *module)
Cell *cell = nullptr;
int j = 0;
int cnt = 0;
IdString names_A[] = { ID(A1), ID(A2), ID(A3), ID(A4) };
IdString names_B[] = { ID(B1), ID(B2), ID(B3), ID(B4) };
IdString names_S[] = { ID(S1), ID(S2), ID(S3), ID(S4) };
TwineRef names_A[] = { TW::A1, TW::A2, TW::A3, TW::A4 };
TwineRef names_B[] = { TW::B1, TW::B2, TW::B3, TW::B4 };
TwineRef names_S[] = { TW::S1, TW::S2, TW::S3, TW::S4 };
if (!c.second.at(0)->getPort(TW::CI).is_fully_const()) {
cell = module->addCell(NEW_TWINE, ID(NX_CY));
cell = module->addCell(NEW_TWINE, TW::NX_CY);
cell->setParam(ID(add_carry), Const(1,2));
cell->setPort(TW::CI, State::S1);
@ -92,7 +92,7 @@ static void nx_carry_chain(Module *module)
for (size_t i=0 ; i<c.second.size(); i++) {
if (j==0) {
cell = module->addCell(NEW_TWINE, ID(NX_CY));
cell = module->addCell(NEW_TWINE, TW::NX_CY);
SigBit ci = c.second.at(i)->getPort(TW::CI).as_bit();
cell->setPort(TW::CI, ci);
if (ci.is_wire()) {
@ -110,7 +110,7 @@ static void nx_carry_chain(Module *module)
cell->setPort(TW::A4, State::S0);
cell->setPort(TW::B4, State::S0);
cell->setPort(TW::S4, new_co);
cell = module->addCell(NEW_TWINE, ID(NX_CY));
cell = module->addCell(NEW_TWINE, TW::NX_CY);
cell->setParam(ID(add_carry), Const(1,2));
cell->setPort(TW::CI, State::S1);
cell->setPort(TW::A1, new_co);

72
techlibs/quicklogic/ql_bram_merge.cc
View file

@ -39,7 +39,7 @@ struct QlBramMergeWorker {
QlBramMergeWorker(RTLIL::Module* module) : module(module)
{
const RTLIL::IdString split_cell_type = TW($__QLF_TDP36K);
const TwineRef split_cell_type = TW($__QLF_TDP36K);
for (RTLIL::Cell* cell : module->selected_cells())
{
@ -81,39 +81,39 @@ struct QlBramMergeWorker {
return bram1_map;
}
const dict<RTLIL::IdString, RTLIL::IdString>& port_map(bool second)
const dict<TwineRef, TwineRef>& port_map(bool second)
{
static const dict<RTLIL::IdString, RTLIL::IdString> bram1_map = {
{ ID(PORT_A_CLK), ID(PORT_A1_CLK) },
{ ID(PORT_B_CLK), ID(PORT_B1_CLK) },
{ ID(PORT_A_CLK_EN), ID(PORT_A1_CLK_EN) },
{ ID(PORT_B_CLK_EN), ID(PORT_B1_CLK_EN) },
{ ID(PORT_A_ADDR), ID(PORT_A1_ADDR) },
{ ID(PORT_B_ADDR), ID(PORT_B1_ADDR) },
{ ID(PORT_A_WR_DATA), ID(PORT_A1_WR_DATA) },
{ ID(PORT_B_WR_DATA), ID(PORT_B1_WR_DATA) },
{ ID(PORT_A_WR_EN), ID(PORT_A1_WR_EN) },
{ ID(PORT_B_WR_EN), ID(PORT_B1_WR_EN) },
{ ID(PORT_A_WR_BE), ID(PORT_A1_WR_BE) },
{ ID(PORT_B_WR_BE), ID(PORT_B1_WR_BE) },
{ ID(PORT_A_RD_DATA), ID(PORT_A1_RD_DATA) },
{ ID(PORT_B_RD_DATA), ID(PORT_B1_RD_DATA) }
static const dict<TwineRef, TwineRef> bram1_map = {
{ TW::PORT_A_CLK, TW::PORT_A1_CLK },
{ TW::PORT_B_CLK, TW::PORT_B1_CLK },
{ TW::PORT_A_CLK_EN, TW::PORT_A1_CLK_EN },
{ TW::PORT_B_CLK_EN, TW::PORT_B1_CLK_EN },
{ TW::PORT_A_ADDR, TW::PORT_A1_ADDR },
{ TW::PORT_B_ADDR, TW::PORT_B1_ADDR },
{ TW::PORT_A_WR_DATA, TW::PORT_A1_WR_DATA },
{ TW::PORT_B_WR_DATA, TW::PORT_B1_WR_DATA },
{ TW::PORT_A_WR_EN, TW::PORT_A1_WR_EN },
{ TW::PORT_B_WR_EN, TW::PORT_B1_WR_EN },
{ TW::PORT_A_WR_BE, TW::PORT_A1_WR_BE },
{ TW::PORT_B_WR_BE, TW::PORT_B1_WR_BE },
{ TW::PORT_A_RD_DATA, TW::PORT_A1_RD_DATA },
{ TW::PORT_B_RD_DATA, TW::PORT_B1_RD_DATA }
};
static const dict<RTLIL::IdString, RTLIL::IdString> bram2_map = {
{ ID(PORT_A_CLK), ID(PORT_A2_CLK) },
{ ID(PORT_B_CLK), ID(PORT_B2_CLK) },
{ ID(PORT_A_CLK_EN), ID(PORT_A2_CLK_EN) },
{ ID(PORT_B_CLK_EN), ID(PORT_B2_CLK_EN) },
{ ID(PORT_A_ADDR), ID(PORT_A2_ADDR) },
{ ID(PORT_B_ADDR), ID(PORT_B2_ADDR) },
{ ID(PORT_A_WR_DATA), ID(PORT_A2_WR_DATA) },
{ ID(PORT_B_WR_DATA), ID(PORT_B2_WR_DATA) },
{ ID(PORT_A_WR_EN), ID(PORT_A2_WR_EN) },
{ ID(PORT_B_WR_EN), ID(PORT_B2_WR_EN) },
{ ID(PORT_A_WR_BE), ID(PORT_A2_WR_BE) },
{ ID(PORT_B_WR_BE), ID(PORT_B2_WR_BE) },
{ ID(PORT_A_RD_DATA), ID(PORT_A2_RD_DATA) },
{ ID(PORT_B_RD_DATA), ID(PORT_B2_RD_DATA) }
static const dict<TwineRef, TwineRef> bram2_map = {
{ TW::PORT_A_CLK, TW::PORT_A2_CLK },
{ TW::PORT_B_CLK, TW::PORT_B2_CLK },
{ TW::PORT_A_CLK_EN, TW::PORT_A2_CLK_EN },
{ TW::PORT_B_CLK_EN, TW::PORT_B2_CLK_EN },
{ TW::PORT_A_ADDR, TW::PORT_A2_ADDR },
{ TW::PORT_B_ADDR, TW::PORT_B2_ADDR },
{ TW::PORT_A_WR_DATA, TW::PORT_A2_WR_DATA },
{ TW::PORT_B_WR_DATA, TW::PORT_B2_WR_DATA },
{ TW::PORT_A_WR_EN, TW::PORT_A2_WR_EN },
{ TW::PORT_B_WR_EN, TW::PORT_B2_WR_EN },
{ TW::PORT_A_WR_BE, TW::PORT_A2_WR_BE },
{ TW::PORT_B_WR_BE, TW::PORT_B2_WR_BE },
{ TW::PORT_A_RD_DATA, TW::PORT_A2_RD_DATA },
{ TW::PORT_B_RD_DATA, TW::PORT_B2_RD_DATA }
};
if(second)
@ -124,11 +124,11 @@ struct QlBramMergeWorker {
void merge_brams(RTLIL::Cell* bram1, RTLIL::Cell* bram2)
{
const RTLIL::IdString merged_cell_type = TW($__QLF_TDP36K_MERGED);
const TwineRef merged_cell_type = TW($__QLF_TDP36K_MERGED);
// Create the new cell
RTLIL::Cell* merged = module->addCell(NEW_TWINE, merged_cell_type);
log_debug("Merging split BRAM cells %s and %s -> %s\n", design->twines.unescaped_str(bram1->name), design->twines.unescaped_str(bram2->name), design->twines.unescaped_str(merged->name));
log_debug("Merging split BRAM cells %s and %s -> %s\n", module->design->twines.unescaped_str(bram1->name.ref()), module->design->twines.unescaped_str(bram2->name.ref()), module->design->twines.unescaped_str(merged->name.ref()));
for (auto &it : param_map(false))
{
@ -146,14 +146,14 @@ struct QlBramMergeWorker {
if (bram1->hasPort(it.first))
merged->setPort(it.second, bram1->getPort(it.first));
else
log_error("Can't find port %s on cell %s!\n", design->twines.unescaped_str(it.first), design->twines.unescaped_str(bram1->name));
log_error("Can't find port %s on cell %s!\n", module->design->twines.unescaped_str(it.first), module->design->twines.unescaped_str(bram1->name.ref()));
}
for (auto &it : port_map(true))
{
if (bram2->hasPort(it.first))
merged->setPort(it.second, bram2->getPort(it.first));
else
log_error("Can't find port %s on cell %s!\n", design->twines.unescaped_str(it.first), design->twines.unescaped_str(bram2->name));
log_error("Can't find port %s on cell %s!\n", module->design->twines.unescaped_str(it.first), module->design->twines.unescaped_str(bram2->name.ref()));
}
merged->attributes = bram1->attributes;
for (auto attr: bram2->attributes)

2
techlibs/quicklogic/ql_bram_types.cc
View file

@ -154,7 +154,7 @@ struct QlBramTypesPass : public Pass {
type += "nonsplit";
}
cell->type = RTLIL::escape_id(type);
cell->type_impl = cell->module->design->twines.add(std::string{RTLIL::escape_id(type)});
log_debug("Changed type of memory cell %s to %s\n", cell->module->design->twines.str(cell->meta_->name), cell->type.unescaped());
}
}

12
techlibs/quicklogic/ql_dsp_io_regs.cc
View file

@ -63,9 +63,9 @@ struct QlDspIORegs : public Pass {
void ql_dsp_io_regs_pass(RTLIL::Module *module)
{
static const std::vector<IdString> ports2del_mult = {ID(load_acc), ID(subtract), ID(acc_fir), ID(dly_b),
ID(saturate_enable), ID(shift_right), ID(round)};
static const std::vector<IdString> ports2del_mult_acc = {ID(acc_fir), ID(dly_b)};
static const std::vector<TwineRef> ports2del_mult = {TW::load_acc, TW::subtract, TW::acc_fir, TW::dly_b,
TW::saturate_enable, TW::shift_right, TW::round};
static const std::vector<TwineRef> ports2del_mult_acc = {TW::acc_fir, TW::dly_b};
sigmap.set(module);
@ -80,10 +80,10 @@ struct QlDspIORegs : public Pass {
continue;
// Get DSP configuration
for (auto cfg_port : {ID(register_inputs), ID(output_select)})
for (auto cfg_port : {TW::register_inputs, TW::output_select})
if (!cell->hasPort(cfg_port) || !sigmap(cell->getPort(cfg_port)).is_fully_const())
log_error("Missing or non-constant '%s' port on DSP cell %s\n",
cfg_port, cell);
cell->module->design->twines.str(cfg_port).c_str(), cell);
int reg_in_i = sigmap(cell->getPort(TW::register_inputs)).as_int();
int out_sel_i = sigmap(cell->getPort(TW::output_select)).as_int();
@ -127,7 +127,7 @@ struct QlDspIORegs : public Pass {
}
// Set new type name
cell->type = RTLIL::IdString(new_type);
cell->type_impl = cell->module->design->twines.add(std::string{new_type});
std::vector<std::string> ports2del;

4
techlibs/quicklogic/ql_dsp_macc.cc
View file

@ -72,8 +72,8 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
return;
}
type = RTLIL::escape_id(cell_base_name + cell_size_name + "_cfg_ports");
log("Inferring MACC %zux%zu->%zu as %s from:\n", a_width, b_width, z_width, design->twines.unescaped_str(type));
type = pm.module->design->twines.add(Twine{RTLIL::escape_id(cell_base_name + cell_size_name + "_cfg_ports")});
log("Inferring MACC %zux%zu->%zu as %s from:\n", a_width, b_width, z_width, pm.module->design->twines.unescaped_str(type));
for (auto cell : {st.mul, st.add, st.mux, st.ff})
if (cell)

4
techlibs/quicklogic/ql_dsp_macc.pmg
View file

@ -9,8 +9,8 @@ pattern ql_dsp_macc
// | |
// --------------
state <IdString> add_ba
state <IdString> mux_ab
state <TwineRef> add_ba
state <TwineRef> mux_ab
// Is the output taken from before or after the FF?
state <bool> output_registered

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