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This commit is contained in:
Emil J. Tywoniak 2026-06-12 00:18:53 +02:00
parent afdae7b87e
commit c3ffbf6fae
229 changed files with 3902 additions and 3835 deletions
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27
frontends/aiger/aigerparse.cc
View file

@ -76,10 +76,10 @@ struct ConstEvalAig
ConstEvalAig(RTLIL::Module *module) : module(module)
{
for (auto &it : module->cells_) {
if (!yosys_celltypes.cell_known(it.second->type))
if (!yosys_celltypes.cell_known(it.second->type.ref()))
continue;
for (auto &it2 : it.second->connections())
if (yosys_celltypes.cell_output(it.second->type, it2.first)) {
if (yosys_celltypes.cell_output(it.second->type.ref(), it2.first)) {
auto r = sig2driver.insert(std::make_pair(it2.second, it.second));
log_assert(r.second);
}
@ -138,7 +138,7 @@ struct ConstEvalAig
if (!inputs.count(sig_a))
compute_deps(sig_a, inputs);
if (cell->type == ID($_AND_)) {
if (cell->type == TW($_AND_)) {
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
sig2deps[sig_b].reserve(sig2deps[sig_b].size() + sig2deps[output].size()); // Reserve so that any invalidation
// that may occur does so here, and
@ -148,7 +148,7 @@ struct ConstEvalAig
if (!inputs.count(sig_b))
compute_deps(sig_b, inputs);
}
else if (cell->type == ID($_NOT_)) {
else if (cell->type == TW($_NOT_)) {
}
else log_abort();
}
@ -164,11 +164,11 @@ struct ConstEvalAig
return false;
RTLIL::State eval_ret = RTLIL::Sx;
if (cell->type == ID($_NOT_)) {
if (cell->type == TW($_NOT_)) {
if (sig_a == State::S0) eval_ret = State::S1;
else if (sig_a == State::S1) eval_ret = State::S0;
}
else if (cell->type == ID($_AND_)) {
else if (cell->type == TW($_AND_)) {
if (sig_a == State::S0) {
eval_ret = State::S0;
goto eval_end;
@ -504,7 +504,8 @@ void AigerReader::parse_xaiger()
uint32_t boxUniqueId = parse_xaiger_literal(f);
log_assert(boxUniqueId > 0);
uint32_t oldBoxNum = parse_xaiger_literal(f);
RTLIL::Cell* cell = module->addCell(Twine{stringf("$box%u", oldBoxNum)}, ID(stringf("$__boxid%u", boxUniqueId)));
TwineRef _type = module->design->twines.add(Twine{stringf("$__boxid%u", boxUniqueId)});
RTLIL::Cell* cell = module->addCell(Twine{stringf("$box%u", oldBoxNum)}, _type);
cell->setPort(TW::I, SigSpec(State::S0, boxInputs));
cell->setPort(TW::O, SigSpec(State::S0, boxOutputs));
cell->attributes[ID::abc9_box_seq] = oldBoxNum;
@ -836,7 +837,7 @@ void AigerReader::post_process()
wire->port_input = false;
module->connect(wire, existing);
}
log_debug(" -> %s\n", escaped_s.unescape());
log_debug(" -> %s\n", design->twines.unescaped_str(escaped_s));
}
else {
RTLIL::IdString indexed_name = stringf("%s[%d]", escaped_s, index);
@ -847,7 +848,7 @@ void AigerReader::post_process()
module->connect(wire, existing);
wire->port_input = false;
}
log_debug(" -> %s\n", indexed_name.unescape());
log_debug(" -> %s\n", design->twines.unescaped_str(indexed_name));
}
if (wideports && !existing) {
@ -883,7 +884,7 @@ void AigerReader::post_process()
module->connect(wire, existing);
wire = existing;
}
log_debug(" -> %s\n", escaped_s.unescape());
log_debug(" -> %s\n", design->twines.unescaped_str(escaped_s));
}
else {
RTLIL::IdString indexed_name = stringf("%s[%d]", escaped_s, index);
@ -895,7 +896,7 @@ void AigerReader::post_process()
existing->port_output = true;
module->connect(wire, existing);
}
log_debug(" -> %s\n", indexed_name.unescape());
log_debug(" -> %s\n", design->twines.unescaped_str(indexed_name));
}
if (wideports && !existing) {
@ -913,7 +914,7 @@ void AigerReader::post_process()
else if (type == "box") {
RTLIL::Cell* cell = module->cell(design->twines.lookup(stringf("$box%d", variable)));
if (!cell)
log_debug("Box %d (%s) no longer exists.\n", variable, escaped_s.unescape());
log_debug("Box %d (%s) no longer exists.\n", variable, design->twines.unescaped_str(escaped_s));
else
module->rename(cell, design->twines.add(Twine{escaped_s.str()}));
}
@ -977,7 +978,7 @@ void AigerReader::post_process()
design->add(module);
for (auto cell : module->cells().to_vector()) {
if (cell->type != ID($lut)) continue;
if (cell->type != TW($lut)) continue;
auto y_port = cell->getPort(TW::Y).as_bit();
if (y_port.wire->width == 1)
module->rename(cell, design->twines.add(Twine{stringf("$lut%s", design->twines.str(y_port.wire->meta_->name).c_str())}));

34
frontends/aiger2/xaiger.cc
View file

@ -28,7 +28,7 @@ uint32_t read_be32(std::istream &f) {
((uint32_t) f.get() << 8) | (uint32_t) f.get();
}
IdString read_idstring(std::istream &f)
std::string read_idstring(std::istream &f)
{
std::string str;
std::getline(f, str, '\0');
@ -61,14 +61,15 @@ struct Xaiger2Frontend : public Frontend {
void read_sc_mapping(std::istream *&f, std::string filename, std::vector<std::string> args, Design *design)
{
IdString module_name;
std::optional<TwineRef> module_name;
TwineSearch search(&design->twines);
std::string map_filename;
size_t argidx;
for (argidx = 2; argidx < args.size(); argidx++) {
std::string arg = args[argidx];
if (arg == "-module_name" && argidx + 1 < args.size()) {
module_name = RTLIL::escape_id(args[++argidx]);
module_name = search.find(RTLIL::escape_id(args[++argidx]));
continue;
}
if (arg == "-map2" && argidx + 1 < args.size()) {
@ -81,12 +82,12 @@ struct Xaiger2Frontend : public Frontend {
if (map_filename.empty())
log_error("A '-map2' argument is required\n");
if (module_name.empty())
if (!module_name)
log_error("A '-module_name' argument is required\n");
Module *module = design->module(module_name);
Module *module = design->module(*module_name);
if (!module)
log_error("Module '%s' not found\n", module_name.unescape());
log_error("Module '%s' not found\n", design->twines.unescaped_str(*module_name));
std::ifstream map_file;
map_file.open(map_filename);
@ -122,7 +123,6 @@ struct Xaiger2Frontend : public Frontend {
bits[1] = RTLIL::S1;
std::string type;
TwineSearch search(&design->twines);
while (map_file >> type) {
if (type == "pi") {
int pi_idx;
@ -159,7 +159,7 @@ struct Xaiger2Frontend : public Frontend {
}
if (!def)
log_error("Bad map file: no module found for box type '%s'\n", box->type.unescape());
log_error("Bad map file: no module found for box type '%s'\n", design->twines.unescaped_str(box->type_impl));
if (box_seq >= (int) boxes.size()) {
boxes.resize(box_seq + 1);
@ -265,22 +265,22 @@ struct Xaiger2Frontend : public Frontend {
struct MappingCell {
TwineRef type;
RTLIL::IdString out;
std::vector<TwineRef ins;
TwineRef out;
std::vector<TwineRef> ins;
};
std::vector<MappingCell> cells;
cells.resize(no_cells);
for (unsigned i = 0; i < no_cells; ++i) {
auto &cell = cells[i];
cell.type = read_idstring(*f);
cell.out = read_idstring(*f);
cell.type = design->twines.add(Twine{read_idstring(*f)});
cell.out = design->twines.add(Twine{read_idstring(*f)});
uint32_t nins = read_be32(*f);
for (uint32_t j = 0; j < nins; j++)
cell.ins.push_back(read_idstring(*f));
log_debug("M: Cell %s (out %s, ins", cell.type.unescape(), cell.out.unescape());
cell.ins.push_back(design->twines.add(Twine{read_idstring(*f)}));
log_debug("M: Cell %s (out %s, ins", design->twines.str(cell.type).c_str(), design->twines.unescaped_str(cell.out));
for (auto in : cell.ins)
log_debug(" %s", in.unescape());
log_debug(" %s", design->twines.str(in).c_str());
log_debug(")\n");
}
@ -294,13 +294,13 @@ struct Xaiger2Frontend : public Frontend {
auto &cell = cells[cell_id];
Cell *instance = module->addCell(module->uniquify(design->twines.add(Twine{stringf("$sc%d", out_lit)})), cell.type);
auto out_w = module->addWire(module->uniquify(design->twines.add(Twine{stringf("$lit%d", out_lit)})));
instance->setPort(design->twines.add(Twine{cell.out.str()}), out_w);
instance->setPort(cell.out, out_w);
bits[out_lit] = out_w;
for (auto in : cell.ins) {
uint32_t in_lit = read_be32(*f);
log_assert(out_lit < bits.size());
log_assert(bits[in_lit] != RTLIL::Sm);
instance->setPort(design->twines.add(Twine{in.str()}), bits[in_lit]);
instance->setPort(in, bits[in_lit]);
}
}
} else if (c == '\n') {

26
frontends/ast/ast.cc
View file

@ -1573,7 +1573,7 @@ void AST::explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule
for (auto w : intfmodule->wires()){
auto loc = module_ast->location;
auto wire = std::make_unique<AstNode>(loc, AST_WIRE, std::make_unique<AstNode>(loc, AST_RANGE, AstNode::mkconst_int(loc, w->width -1, true), AstNode::mkconst_int(loc, 0, true)));
std::string origname = w->name.unescape();
std::string origname = intfmodule->design->twines.unescaped_str(w->meta_->name);
std::string newname = intfname + "." + origname;
wire->str = newname;
if (modport != NULL) {
@ -1637,7 +1637,7 @@ void AstModule::expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdStr
RTLIL::Module *intfmodule = intf.second;
for (auto w : intfmodule->wires()){
auto wire = std::make_unique<AstNode>(loc, AST_WIRE, std::make_unique<AstNode>(loc, AST_RANGE, AstNode::mkconst_int(loc, w->width -1, true), AstNode::mkconst_int(loc, 0, true)));
std::string newname = w->name.unescape();
std::string newname = design->twines.unescaped_str(w->meta_->name);
newname = intfname + "." + newname;
wire->str = newname;
new_ast->children.push_back(std::move(wire));
@ -1698,7 +1698,7 @@ void AstModule::expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdStr
// create a new parametric module (when needed) and return the name of the generated module - WITH support for interfaces
// This method is used to explode the interface when the interface is a port of the module (not instantiated inside)
RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool /*mayfail*/)
TwineRef AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<TwineRef, RTLIL::Module*> &interfaces, const dict<TwineRef, TwineRef> &modports, bool /*mayfail*/)
{
std::unique_ptr<AstNode> new_ast = NULL;
std::string modname = derive_common(design, parameters, &new_ast);
@ -1731,11 +1731,11 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
// Iterate over all interfaces which are ports in this module:
for(auto &intf : interfaces) {
RTLIL::Module * intfmodule = intf.second;
std::string intfname = intf.first.str();
std::string intfname = design->twines.str(intf.first);
// Check if a modport applies for the interface port:
AstNode *modport = NULL;
if (modports.count(intfname) > 0) {
std::string interface_modport = modports.at(intfname).str();
if (modports.count(intf.first) > 0) {
std::string interface_modport = design->twines.str(modports.at(intf.first));
AstModule *ast_module_of_interface = (AstModule*)intfmodule;
AstNode *ast_node_of_interface = ast_module_of_interface->ast.get();
modport = find_modport(ast_node_of_interface, interface_modport);
@ -1751,7 +1751,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
// Now that the interfaces have been exploded, we can delete the dummy port related to every interface.
for(auto &intf : interfaces) {
TwineRef intf_name = design->twines.lookup(intf.first.str());
TwineRef intf_name = design->twines.lookup(design->twines.str(intf.first));
if(mod->wire(intf_name) != nullptr) {
// Normally, removing wires would be batched together as it's an
// expensive operation, however, in this case doing so would mean
@ -1764,7 +1764,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
mod->fixup_ports();
// We copy the cell of the interface to the sub-module such that it
// can further be found if it is propagated down to sub-sub-modules etc.
RTLIL::Cell *new_subcell = mod->addCell(Twine{intf.first.str()}, RTLIL::IdString(design->twines.str(intf.second->meta_->name)));
RTLIL::Cell *new_subcell = mod->addCell(intf.first, intf.second->meta_->name);
new_subcell->set_bool_attribute(ID::is_interface);
}
else {
@ -1782,11 +1782,11 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
log("Found cached RTLIL representation for module `%s'.\n", modname);
}
return modname;
return design->twines.add(Twine{modname});
}
// create a new parametric module (when needed) and return the name of the generated module - without support for interfaces
RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool /*mayfail*/)
TwineRef AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool /*mayfail*/)
{
bool quiet = lib || attributes.count(ID::blackbox) || attributes.count(ID::whitebox);
@ -1802,7 +1802,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
log("Found cached RTLIL representation for module `%s'.\n", modname);
}
return modname;
return design->twines.add(Twine{modname});
}
static std::string serialize_param_value(const RTLIL::Const &val) {
@ -1979,11 +1979,11 @@ RTLIL::Module *AstModule::clone(RTLIL::Design *dst, bool src_id_verbatim) const
return new_mod;
}
RTLIL::Module *AstModule::clone(RTLIL::Design *dst, RTLIL::IdString target_name, bool src_id_verbatim) const
RTLIL::Module *AstModule::clone(RTLIL::Design *dst, TwineRef target_name, bool src_id_verbatim) const
{
AstModule *new_mod = new AstModule;
new_mod->design = dst;
new_mod->meta_->name = dst->twines.add(Twine{target_name.str()});
new_mod->meta_->name = target_name;
cloneInto(new_mod, src_id_verbatim);
dst->add(new_mod);

2
frontends/ast/ast.h
View file

@ -397,7 +397,7 @@ namespace AST
std::unique_ptr<AstNode> ast;
bool nolatches, nomeminit, nomem2reg, mem2reg, noblackbox, lib, nowb, noopt, icells, pwires, autowire;
TwineRef derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail) override;
TwineRef derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<TwineRef, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail) override;
TwineRef derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<TwineRef, RTLIL::Module*> &interfaces, const dict<TwineRef, TwineRef> &modports, bool mayfail) override;
std::string derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, std::unique_ptr<AstNode>* new_ast_out, bool quiet = false);
void expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces) override;
bool reprocess_if_necessary(RTLIL::Design *design) override;

116
frontends/ast/genrtlil.cc
View file

@ -27,6 +27,7 @@
*/
#include "kernel/log.h"
#include "kernel/twine.h"
#include "kernel/utils.h"
#include "kernel/binding.h"
#include "libs/sha1/sha1.h"
@ -43,13 +44,13 @@ using namespace AST;
using namespace AST_INTERNAL;
// helper function for creating RTLIL code for unary operations
static RTLIL::SigSpec uniop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)
static RTLIL::SigSpec uniop2rtlil(AstNode *that, TwineRef type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)
{
IdString name = stringf("%s$%s:%d$%d", type, RTLIL::encode_filename(*that->location.begin.filename), that->location.begin.line, autoidx++);
RTLIL::Cell *cell = current_module->addCell(Twine{name.str()}, type);
set_src_attr(cell, that);
RTLIL::Wire *wire = current_module->addWire(Twine{cell->name.str() + "_Y"}, result_width);
RTLIL::Wire *wire = current_module->addWire(Twine{Twine::Suffix{cell->meta_->name, "_Y"}}, result_width);
set_src_attr(wire, that);
wire->is_signed = that->is_signed;
@ -78,7 +79,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
}
IdString name = stringf("$extend$%s:%d$%d", RTLIL::encode_filename(*that->location.begin.filename), that->location.begin.line, autoidx++);
RTLIL::Cell *cell = current_module->addCell(Twine{name.str()}, ID($pos));
RTLIL::Cell *cell = current_module->addCell(Twine{name.str()}, TW::$pos);
set_src_attr(cell, that);
RTLIL::Wire *wire = current_module->addWire(Twine{cell->name.str() + "_Y"}, width);
@ -102,13 +103,13 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
}
// helper function for creating RTLIL code for binary operations
static RTLIL::SigSpec binop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
static RTLIL::SigSpec binop2rtlil(AstNode *that, TwineRef type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
{
IdString name = stringf("%s$%s:%d$%d", type, RTLIL::encode_filename(*that->location.begin.filename), that->location.begin.line, autoidx++);
RTLIL::Cell *cell = current_module->addCell(Twine{name.str()}, type);
set_src_attr(cell, that);
RTLIL::Wire *wire = current_module->addWire(Twine{cell->name.str() + "_Y"}, result_width);
RTLIL::Wire *wire = current_module->addWire(Twine{Twine::Suffix{cell->meta_->name, "_Y"}}, result_width);
set_src_attr(wire, that);
wire->is_signed = that->is_signed;
@ -140,7 +141,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
std::stringstream sstr;
sstr << "$ternary$" << RTLIL::encode_filename(*that->location.begin.filename) << ":" << that->location.begin.line << "$" << (autoidx++);
RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, ID($mux));
RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, TW::$mux);
set_src_attr(cell, that);
RTLIL::Wire *wire = current_module->addWire(Twine{cell->name.str() + "_Y"}, left.size());
@ -837,7 +838,7 @@ struct AST_INTERNAL::ProcessGenerator
}
RTLIL::Const polarity = polarity_builder.build();
RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, ID($print));
RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, TW::$print);
set_src_attr(cell, ast);
cell->setParam(ID::TRG_WIDTH, triggers.size());
cell->setParam(ID::TRG_ENABLE, (always->type == AST_INITIAL) || !triggers.empty());
@ -935,7 +936,7 @@ struct AST_INTERNAL::ProcessGenerator
}
RTLIL::Const polarity = polarity_builder.build();
RTLIL::Cell *cell = current_module->addCell(Twine{cellname.str()}, ID($check));
RTLIL::Cell *cell = current_module->addCell(Twine{cellname.str()}, TW::$check);
set_src_attr(cell, ast);
cell->set_bool_attribute(ID(keep));
for (auto &attr : ast->attributes) {
@ -1443,7 +1444,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// Clifford's Device (http://www.clifford.at/cfun/cliffdev/). In this
// cases this variable is used to hold the type of the cell that should
// be instantiated for this type of AST node.
IdString type_name;
TwineRef type_name;
switch (type)
{
@ -1735,7 +1736,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
}
if (GetSize(shift_val) >= 32)
fake_ast->children[1]->is_signed = true;
RTLIL::SigSpec sig = binop2rtlil(fake_ast.get(), ID($shiftx), width, fake_ast->children[0]->genRTLIL(), shift_val);
RTLIL::SigSpec sig = binop2rtlil(fake_ast.get(), TW($shiftx), width, fake_ast->children[0]->genRTLIL(), shift_val);
return sig;
} else {
chunk.width = children[0]->range_left - children[0]->range_right + 1;
@ -1841,9 +1842,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
input_error("Assignment pattern is only supported for whole unpacked array assignments.\n");
// generate cells for unary operations: $not, $pos, $neg
if (0) { case AST_BIT_NOT: type_name = ID($not); }
if (0) { case AST_POS: type_name = ID($pos); }
if (0) { case AST_NEG: type_name = ID($neg); }
if (0) { case AST_BIT_NOT: type_name = TW($not); }
if (0) { case AST_POS: type_name = TW($pos); }
if (0) { case AST_NEG: type_name = TW($neg); }
{
RTLIL::SigSpec arg = children[0]->genRTLIL(width_hint, sign_hint);
is_signed = children[0]->is_signed;
@ -1856,10 +1857,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
}
// generate cells for binary operations: $and, $or, $xor, $xnor
if (0) { case AST_BIT_AND: type_name = ID($and); }
if (0) { case AST_BIT_OR: type_name = ID($or); }
if (0) { case AST_BIT_XOR: type_name = ID($xor); }
if (0) { case AST_BIT_XNOR: type_name = ID($xnor); }
if (0) { case AST_BIT_AND: type_name = TW($and); }
if (0) { case AST_BIT_OR: type_name = TW($or); }
if (0) { case AST_BIT_XOR: type_name = TW($xor); }
if (0) { case AST_BIT_XNOR: type_name = TW($xnor); }
{
if (width_hint < 0)
detectSignWidth(width_hint, sign_hint);
@ -1873,10 +1874,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
}
// generate cells for unary operations: $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor
if (0) { case AST_REDUCE_AND: type_name = ID($reduce_and); }
if (0) { case AST_REDUCE_OR: type_name = ID($reduce_or); }
if (0) { case AST_REDUCE_XOR: type_name = ID($reduce_xor); }
if (0) { case AST_REDUCE_XNOR: type_name = ID($reduce_xnor); }
if (0) { case AST_REDUCE_AND: type_name = TW($reduce_and); }
if (0) { case AST_REDUCE_OR: type_name = TW($reduce_or); }
if (0) { case AST_REDUCE_XOR: type_name = TW($reduce_xor); }
if (0) { case AST_REDUCE_XNOR: type_name = TW($reduce_xnor); }
{
RTLIL::SigSpec arg = children[0]->genRTLIL();
RTLIL::SigSpec sig = uniop2rtlil(this, type_name, max(width_hint, 1), arg);
@ -1885,7 +1886,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// generate cells for unary operations: $reduce_bool
// (this is actually just an $reduce_or, but for clarity a different cell type is used)
if (0) { case AST_REDUCE_BOOL: type_name = ID($reduce_bool); }
if (0) { case AST_REDUCE_BOOL: type_name = TW($reduce_bool); }
{
RTLIL::SigSpec arg = children[0]->genRTLIL();
RTLIL::SigSpec sig = arg.size() > 1 ? uniop2rtlil(this, type_name, max(width_hint, 1), arg) : arg;
@ -1893,12 +1894,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
}
// generate cells for binary operations: $shl, $shr, $sshl, $sshr
if (0) { case AST_SHIFT_LEFT: type_name = ID($shl); }
if (0) { case AST_SHIFT_RIGHT: type_name = ID($shr); }
if (0) { case AST_SHIFT_SLEFT: type_name = ID($sshl); }
if (0) { case AST_SHIFT_SRIGHT: type_name = ID($sshr); }
if (0) { case AST_SHIFTX: type_name = ID($shiftx); }
if (0) { case AST_SHIFT: type_name = ID($shift); }
if (0) { case AST_SHIFT_LEFT: type_name = TW($shl); }
if (0) { case AST_SHIFT_RIGHT: type_name = TW($shr); }
if (0) { case AST_SHIFT_SLEFT: type_name = TW($sshl); }
if (0) { case AST_SHIFT_SRIGHT: type_name = TW($sshr); }
if (0) { case AST_SHIFTX: type_name = TW($shiftx); }
if (0) { case AST_SHIFT: type_name = TW($shift); }
{
if (width_hint < 0)
detectSignWidth(width_hint, sign_hint);
@ -1923,19 +1924,19 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
int width = width_hint > 0 ? width_hint : left.size();
is_signed = children[0]->is_signed;
if (!flag_noopt && left.is_fully_const() && left.as_int() == 2 && !right_signed)
return binop2rtlil(this, ID($shl), width, RTLIL::SigSpec(1, left.size()), right);
return binop2rtlil(this, ID($pow), width, left, right);
return binop2rtlil(this, TW($shl), width, RTLIL::SigSpec(1, left.size()), right);
return binop2rtlil(this, TW($pow), width, left, right);
}
// generate cells for binary operations: $lt, $le, $eq, $ne, $ge, $gt
if (0) { case AST_LT: type_name = ID($lt); }
if (0) { case AST_LE: type_name = ID($le); }
if (0) { case AST_EQ: type_name = ID($eq); }
if (0) { case AST_NE: type_name = ID($ne); }
if (0) { case AST_EQX: type_name = ID($eqx); }
if (0) { case AST_NEX: type_name = ID($nex); }
if (0) { case AST_GE: type_name = ID($ge); }
if (0) { case AST_GT: type_name = ID($gt); }
if (0) { case AST_LT: type_name = TW($lt); }
if (0) { case AST_LE: type_name = TW($le); }
if (0) { case AST_EQ: type_name = TW($eq); }
if (0) { case AST_NE: type_name = TW($ne); }
if (0) { case AST_EQX: type_name = TW($eqx); }
if (0) { case AST_NEX: type_name = TW($nex); }
if (0) { case AST_GE: type_name = TW($ge); }
if (0) { case AST_GT: type_name = TW($gt); }
{
int width = max(width_hint, 1);
width_hint = -1, sign_hint = true;
@ -1948,11 +1949,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
}
// generate cells for binary operations: $add, $sub, $mul, $div, $mod
if (0) { case AST_ADD: type_name = ID($add); }
if (0) { case AST_SUB: type_name = ID($sub); }
if (0) { case AST_MUL: type_name = ID($mul); }
if (0) { case AST_DIV: type_name = ID($div); }
if (0) { case AST_MOD: type_name = ID($mod); }
if (0) { case AST_ADD: type_name = TW($add); }
if (0) { case AST_SUB: type_name = TW($sub); }
if (0) { case AST_MUL: type_name = TW($mul); }
if (0) { case AST_DIV: type_name = TW($div); }
if (0) { case AST_MOD: type_name = TW($mod); }
{
if (width_hint < 0)
detectSignWidth(width_hint, sign_hint);
@ -1978,8 +1979,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
}
// generate cells for binary operations: $logic_and, $logic_or
if (0) { case AST_LOGIC_AND: type_name = ID($logic_and); }
if (0) { case AST_LOGIC_OR: type_name = ID($logic_or); }
if (0) { case AST_LOGIC_AND: type_name = TW($logic_and); }
if (0) { case AST_LOGIC_OR: type_name = TW($logic_or); }
{
RTLIL::SigSpec left = children[0]->genRTLIL();
RTLIL::SigSpec right = children[1]->genRTLIL();
@ -1990,7 +1991,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_LOGIC_NOT:
{
RTLIL::SigSpec arg = children[0]->genRTLIL();
return uniop2rtlil(this, ID($logic_not), max(width_hint, 1), arg);
return uniop2rtlil(this, TW($logic_not), max(width_hint, 1), arg);
}
// generate multiplexer for ternary operator (aka ?:-operator)
@ -2021,7 +2022,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint);
if (cond.size() > 1)
cond = uniop2rtlil(this, ID($reduce_bool), 1, cond, false);
cond = uniop2rtlil(this, TW($reduce_bool), 1, cond, false);
int width = max(val1.size(), val2.size());
log_assert(is_signed == children[1]->is_signed);
@ -2043,7 +2044,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
std::stringstream sstr;
sstr << "$memrd$" << str << "$" << RTLIL::encode_filename(*location.begin.filename) << ":" << location.begin.line << "$" << (autoidx++);
RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, ID($memrd));
RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, TW::$memrd);
set_src_attr(cell, this);
RTLIL::Wire *wire = current_module->addWire(Twine{cell->name.str() + "_DATA"}, current_module->memories[current_module->design->twines.lookup(str)]->width);
@ -2083,7 +2084,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
SigSpec en_sig = children[2]->genRTLIL();
RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, ID($meminit_v2));
RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, TW::$meminit_v2);
set_src_attr(cell, this);
int mem_width, mem_size, addr_bits;
@ -2133,7 +2134,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (GetSize(check) != 1)
check = current_module->ReduceBool(NEW_TWINE, check);
RTLIL::Cell *cell = current_module->addCell(Twine{cellname.str()}, ID($check));
RTLIL::Cell *cell = current_module->addCell(Twine{cellname.str()}, TW::$check);
set_src_attr(cell, this);
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)
@ -2185,7 +2186,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
RTLIL::IdString id = str;
check_unique_id(current_module, id, this, "cell");
RTLIL::Cell *cell = current_module->addCell(Twine{id.str()}, "");
RTLIL::Cell *cell = current_module->addCell(Twine{id.str()}, Twine::Null);
set_src_attr(cell, this);
for (auto it = children.begin(); it != children.end(); it++) {
@ -2202,10 +2203,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
const auto* value = child->children[0].get();
if (value->type == AST_REALVALUE)
log_file_warning(*location.begin.filename, location.begin.line, "Replacing floating point parameter %s.%s = %f with string.\n",
cell, paraname.unescape(), value->realvalue);
cell, design->twines.unescaped_str(paraname), value->realvalue);
else if (value->type != AST_CONSTANT)
input_error("Parameter %s.%s with non-constant value!\n",
cell, paraname.unescape());
cell, design->twines.unescaped_str(paraname));
cell->parameters[paraname] = value->asParaConst();
continue;
}
@ -2260,7 +2261,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
input_error("Attribute `%s' with non-constant value.\n", attr.first);
cell->attributes[attr.first] = attr.second->asAttrConst();
}
if (cell->type == ID($specify2)) {
if (cell->type == TW($specify2)) {
int src_width = GetSize(cell->getPort(TW::SRC));
int dst_width = GetSize(cell->getPort(TW::DST));
bool full = cell->getParam(ID::FULL).as_bool();
@ -2269,7 +2270,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
cell->setParam(ID::SRC_WIDTH, Const(src_width));
cell->setParam(ID::DST_WIDTH, Const(dst_width));
}
else if (cell->type == ID($specify3)) {
else if (cell->type == TW($specify3)) {
int dat_width = GetSize(cell->getPort(TW::DAT));
int dst_width = GetSize(cell->getPort(TW::DST));
if (dat_width != dst_width)
@ -2278,7 +2279,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
cell->setParam(ID::SRC_WIDTH, Const(src_width));
cell->setParam(ID::DST_WIDTH, Const(dst_width));
}
else if (cell->type == ID($specrule)) {
else if (cell->type == TW($specrule)) {
int src_width = GetSize(cell->getPort(TW::SRC));
int dst_width = GetSize(cell->getPort(TW::DST));
cell->setParam(ID::SRC_WIDTH, Const(src_width));
@ -2356,7 +2357,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (width <= 0)
input_error("Failed to detect width of %s!\n", RTLIL::unescape_id(str));
Cell *cell = current_module->addCell(Twine{myid}, str.substr(1));
TwineRef _type = current_module->design->twines.add(Twine{str.substr(1)});
Cell *cell = current_module->addCell(Twine{myid}, _type);
set_src_attr(cell, this);
cell->parameters[ID::WIDTH] = width;

12
frontends/blif/blifparse.cc
View file

@ -228,7 +228,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
vector<Cell*> remove_cells;
for (auto cell : module->cells())
if (cell->type == ID($lut) && cell->getParam(ID::LUT) == buffer_lut) {
if (cell->type == TW($lut) && cell->getParam(ID::LUT) == buffer_lut) {
module->connect(cell->getPort(TW::Y), cell->getPort(TW::A));
remove_cells.push_back(cell);
}
@ -381,7 +381,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
if (dff_name.empty()) {
cell = module->addFfGate(NEW_TWINE, blif_wire(d), blif_wire(q));
} else {
cell = module->addCell(NEW_TWINE, dff_name);
cell = module->addCell(NEW_TWINE, design->twines.add(Twine{dff_name.str()}));
cell->setPort(TW::D, blif_wire(d));
cell->setPort(TW::Q, blif_wire(q));
}
@ -400,7 +400,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
goto error;
IdString celltype = RTLIL::escape_id(p);
RTLIL::Cell *cell = module->addCell(NEW_TWINE, celltype);
RTLIL::Cell *cell = module->addCell(NEW_TWINE, design->twines.add(Twine{celltype.str()}));
RTLIL::Module *cell_mod = design->module(celltype);
dict<TwineRef, dict<int, SigBit>> cell_wideports_cache;
@ -542,7 +542,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
finished_parsing_constval:
if (state == RTLIL::State::Sa)
state = RTLIL::State::S0;
if (output_sig.as_wire()->name == ID($undef))
if (output_sig.as_wire()->name == TW($undef))
state = RTLIL::State::Sx;
module->connect(RTLIL::SigSig(output_sig, state));
goto continue_without_read;
@ -550,7 +550,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
if (sop_mode)
{
sopcell = module->addCell(NEW_TWINE, ID($sop));
sopcell = module->addCell(NEW_TWINE, TW::$sop);
sopcell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size());
sopcell->parameters[ID::DEPTH] = 0;
sopcell->parameters[ID::TABLE] = RTLIL::Const();
@ -566,7 +566,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
}
else
{
RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($lut));
RTLIL::Cell *cell = module->addCell(NEW_TWINE, TW::$lut);
cell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size());
cell->parameters[ID::LUT] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size());
cell->setPort(TW::A, input_sig);

2
frontends/json/jsonparse.cc
View file

@ -532,7 +532,7 @@ void json_import(Design *design, string &modname, JsonNode *node)
IdString cell_type = RTLIL::escape_id(type_node->data_string.c_str());
Cell *cell = module->addCell(Twine{cell_name.str()}, cell_type);
Cell *cell = module->addCell(Twine{cell_name.str()}, Twine{cell_type.str()});
if (cell_node->data_dict.count("connections") == 0)
log_error("JSON cells node '%s' has no connections attribute.\n", cell_name.unescape());

35
frontends/liberty/liberty.cc
View file

@ -186,7 +186,7 @@ static RTLIL::SigSpec create_tristate(RTLIL::Module *module, RTLIL::SigSpec func
{
RTLIL::SigSpec three_state = parse_func_expr(module, three_state_expr);
RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($tribuf));
RTLIL::Cell *cell = module->addCell(NEW_TWINE, TW::$tribuf);
cell->setParam(ID::WIDTH, GetSize(func));
cell->setPort(TW::A, func);
cell->setPort(TW::EN, module->NotGate(NEW_TWINE, three_state));
@ -246,17 +246,17 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node)
rerun_invert_rollback = false;
for (auto &it : module->cells_) {
if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == clk_sig) {
if (it.second->type == TW($_NOT_) && it.second->getPort(TW::Y) == clk_sig) {
clk_sig = it.second->getPort(TW::A);
clk_polarity = !clk_polarity;
rerun_invert_rollback = true;
}
if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == clear_sig) {
if (it.second->type == TW($_NOT_) && it.second->getPort(TW::Y) == clear_sig) {
clear_sig = it.second->getPort(TW::A);
clear_polarity = !clear_polarity;
rerun_invert_rollback = true;
}
if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == preset_sig) {
if (it.second->type == TW($_NOT_) && it.second->getPort(TW::Y) == preset_sig) {
preset_sig = it.second->getPort(TW::A);
preset_polarity = !preset_polarity;
rerun_invert_rollback = true;
@ -271,7 +271,7 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node)
module->addNotGate(NEW_TWINE, q_sig, out_sig);
}
RTLIL::Cell* cell = module->addCell(NEW_TWINE, "");
RTLIL::Cell* cell = module->addCell(NEW_TWINE, Twine::Null);
cell->setPort(TW::D, data_sig);
cell->setPort(TW::Q, q_sig);
cell->setPort(TW::C, clk_sig);
@ -355,17 +355,17 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
rerun_invert_rollback = false;
for (auto &it : module->cells_) {
if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == enable_sig) {
if (it.second->type == TW($_NOT_) && it.second->getPort(TW::Y) == enable_sig) {
enable_sig = it.second->getPort(TW::A);
enable_polarity = !enable_polarity;
rerun_invert_rollback = true;
}
if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == clear_sig) {
if (it.second->type == TW($_NOT_) && it.second->getPort(TW::Y) == clear_sig) {
clear_sig = it.second->getPort(TW::A);
clear_polarity = !clear_polarity;
rerun_invert_rollback = true;
}
if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == preset_sig) {
if (it.second->type == TW($_NOT_) && it.second->getPort(TW::Y) == preset_sig) {
preset_sig = it.second->getPort(TW::A);
preset_polarity = !preset_polarity;
rerun_invert_rollback = true;
@ -373,7 +373,7 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
}
}
RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($_NOT_));
RTLIL::Cell *cell = module->addCell(NEW_TWINE, TW::$_NOT_);
cell->setPort(TW::A, iq_sig);
cell->setPort(TW::Y, iqn_sig);
@ -384,7 +384,7 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
if (clear_polarity == true || clear_polarity != enable_polarity)
{
RTLIL::Cell *inv = module->addCell(NEW_TWINE, ID($_NOT_));
RTLIL::Cell *inv = module->addCell(NEW_TWINE, TW::$_NOT_);
inv->setPort(TW::A, clear_sig);
inv->setPort(TW::Y, module->addWire(NEW_TWINE));
@ -394,12 +394,12 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
clear_enable = inv->getPort(TW::Y);
}
RTLIL::Cell *data_gate = module->addCell(NEW_TWINE, ID($_AND_));
RTLIL::Cell *data_gate = module->addCell(NEW_TWINE, TW::$_AND_);
data_gate->setPort(TW::A, data_sig);
data_gate->setPort(TW::B, clear_negative);
data_gate->setPort(TW::Y, data_sig = module->addWire(NEW_TWINE));
RTLIL::Cell *enable_gate = module->addCell(NEW_TWINE, enable_polarity ? ID($_OR_) : ID($_AND_));
RTLIL::Cell *enable_gate = module->addCell(NEW_TWINE, enable_polarity ? TW::$_OR_ : TW::$_AND_);
enable_gate->setPort(TW::A, enable_sig);
enable_gate->setPort(TW::B, clear_enable);
enable_gate->setPort(TW::Y, enable_sig = module->addWire(NEW_TWINE));
@ -412,7 +412,7 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
if (preset_polarity == false || preset_polarity != enable_polarity)
{
RTLIL::Cell *inv = module->addCell(NEW_TWINE, ID($_NOT_));
RTLIL::Cell *inv = module->addCell(NEW_TWINE, TW::$_NOT_);
inv->setPort(TW::A, preset_sig);
inv->setPort(TW::Y, module->addWire(NEW_TWINE));
@ -422,18 +422,19 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
preset_enable = inv->getPort(TW::Y);
}
RTLIL::Cell *data_gate = module->addCell(NEW_TWINE, ID($_OR_));
RTLIL::Cell *data_gate = module->addCell(NEW_TWINE, TW::$_OR_);
data_gate->setPort(TW::A, data_sig);
data_gate->setPort(TW::B, preset_positive);
data_gate->setPort(TW::Y, data_sig = module->addWire(NEW_TWINE));
RTLIL::Cell *enable_gate = module->addCell(NEW_TWINE, enable_polarity ? ID($_OR_) : ID($_AND_));
RTLIL::Cell *enable_gate = module->addCell(NEW_TWINE, enable_polarity ? TW::$_OR_ : TW::$_AND_);
enable_gate->setPort(TW::A, enable_sig);
enable_gate->setPort(TW::B, preset_enable);
enable_gate->setPort(TW::Y, enable_sig = module->addWire(NEW_TWINE));
}
cell = module->addCell(NEW_TWINE, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N'));
TwineRef _t = module->design->twines.add(Twine{stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N')});
cell = module->addCell(NEW_TWINE, _t);
cell->setPort(TW::D, data_sig);
cell->setPort(TW::Q, iq_sig);
cell->setPort(TW::E, enable_sig);
@ -798,7 +799,7 @@ struct LibertyFrontend : public Frontend {
if (wi->port_input) {
for (auto wo : module->wires())
if (wo->port_output) {
RTLIL::Cell *spec = module->addCell(NEW_TWINE, ID($specify2));
RTLIL::Cell *spec = module->addCell(NEW_TWINE, TW::$specify2);
spec->setParam(ID::SRC_WIDTH, wi->width);
spec->setParam(ID::DST_WIDTH, wo->width);
spec->setParam(ID::T_FALL_MAX, 1000);

6
frontends/rpc/rpc_frontend.cc
View file

@ -157,7 +157,7 @@ struct RpcServer {
struct RpcModule : RTLIL::Module {
std::shared_ptr<RpcServer> server;
RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool /*mayfail*/) override {
TwineRef derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool /*mayfail*/) override {
std::string stripped_name = design->twines.str(meta_->name);
if (stripped_name.compare(0, 9, "$abstract") == 0)
stripped_name = stripped_name.substr(9);
@ -215,7 +215,7 @@ struct RpcModule : RTLIL::Module {
log("Importing `%s' as `%s'.\n", derived_design->twines.str(module.first), mangled_name);
RTLIL::IdString original_name = RTLIL::IdString(derived_design->twines.str(module.first));
RTLIL::Module *t = module.second->clone(design, RTLIL::IdString(mangled_name));
RTLIL::Module *t = module.second->clone(design, design->twines.add(Twine{mangled_name}));
t->attributes.erase(ID::top);
if (!t->has_attribute(ID::hdlname))
t->set_string_attribute(ID::hdlname, original_name.str());
@ -224,7 +224,7 @@ struct RpcModule : RTLIL::Module {
delete derived_design;
}
return derived_name;
return design->twines.add(Twine{derived_name});
}
RTLIL::Module *clone() const override {

4
frontends/rtlil/rtlil_frontend.cc
View file

@ -341,7 +341,7 @@ struct RTLILFrontendWorker {
error("No wires found for legalization");
int hash = hash_ops<RTLIL::IdString>::hash(id).yield();
RTLIL::Wire *wire = current_module->wire_at(abs(hash % wires_size));
log("Legalizing wire `%s' to `%s'.\n", id.unescape(), wire->name.unescape());
log("Legalizing wire `%s' to `%s'.\n", design->twines.unescaped_str(id), design->twines.unescaped_str(wire->name));
return wire;
}
@ -748,7 +748,7 @@ struct RTLILFrontendWorker {
} else
error("RTLIL error: redefinition of cell %s.", cell_name_str);
}
RTLIL::Cell *cell = current_module->addCell(Twine{cell_name_str}, cell_type);
RTLIL::Cell *cell = current_module->addCell(cell_name_ref, design->twines.add(Twine{cell_type.str()}));
cell->absorb_attrs(std::move(attrbuf));
while (true)