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https://github.com/YosysHQ/yosys
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rtlil: fix masquerade
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parent
2d3b7e9c92
commit
1a8a95b472
11 changed files with 77 additions and 39 deletions
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@ -1931,6 +1931,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
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RTLIL::Module *AstModule::clone() const
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{
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AstModule *new_mod = new AstModule;
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new_mod->design = design;
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new_mod->name = name;
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cloneInto(new_mod);
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@ -1955,8 +1956,32 @@ RTLIL::Module *AstModule::clone(RTLIL::Design *dst, bool src_id_verbatim) const
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AstModule *new_mod = new AstModule;
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new_mod->design = dst;
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new_mod->name = name;
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dst->add(new_mod);
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cloneInto(new_mod, src_id_verbatim);
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dst->add(new_mod);
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new_mod->ast = ast->clone();
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new_mod->nolatches = nolatches;
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new_mod->nomeminit = nomeminit;
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new_mod->nomem2reg = nomem2reg;
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new_mod->mem2reg = mem2reg;
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new_mod->noblackbox = noblackbox;
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new_mod->lib = lib;
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new_mod->nowb = nowb;
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new_mod->noopt = noopt;
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new_mod->icells = icells;
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new_mod->pwires = pwires;
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new_mod->autowire = autowire;
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return new_mod;
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}
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RTLIL::Module *AstModule::clone(RTLIL::Design *dst, RTLIL::IdString target_name, bool src_id_verbatim) const
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{
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AstModule *new_mod = new AstModule;
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new_mod->design = dst;
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new_mod->name = target_name;
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cloneInto(new_mod, src_id_verbatim);
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dst->add(new_mod);
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new_mod->ast = ast->clone();
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new_mod->nolatches = nolatches;
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@ -403,6 +403,7 @@ namespace AST
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bool reprocess_if_necessary(RTLIL::Design *design) override;
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RTLIL::Module *clone() const override;
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RTLIL::Module *clone(RTLIL::Design *dst, bool src_id_verbatim = false) const override;
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RTLIL::Module *clone(RTLIL::Design *dst, RTLIL::IdString target_name, bool src_id_verbatim = false) const override;
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void loadconfig() const;
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};
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@ -214,13 +214,11 @@ struct RpcModule : RTLIL::Module {
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log("Importing `%s' as `%s'.\n", module.first.unescape(), mangled_name);
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module.second->name = mangled_name;
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module.second->design = design;
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module.second->attributes.erase(ID::top);
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if (!module.second->has_attribute(ID::hdlname))
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module.second->set_string_attribute(ID::hdlname, module.first.str());
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design->modules_[mangled_name] = module.second;
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derived_design->modules_.erase(module.first);
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RTLIL::IdString original_name = module.first;
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RTLIL::Module *t = module.second->clone(design, RTLIL::IdString(mangled_name));
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t->attributes.erase(ID::top);
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if (!t->has_attribute(ID::hdlname))
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t->set_string_attribute(ID::hdlname, original_name.str());
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}
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delete derived_design;
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@ -588,6 +586,7 @@ cleanup_path:
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for (auto &module_name : server->get_module_names()) {
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log("Linking module `%s'.\n", module_name);
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RpcModule *module = new RpcModule;
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module->design = design;
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module->name = "$abstract\\" + module_name;
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module->server = server;
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design->add(module);
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