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rtlil: evacuate src_id_ from AttrObject to per-Design meta vector

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This commit is contained in:
Emil J. Tywoniak 2026-06-05 14:15:51 +02:00
parent e70eed3296
commit f1edb571f2
22 changed files with 668 additions and 390 deletions
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6
frontends/ast/ast.cc
View file

@ -1114,7 +1114,7 @@ void AST::set_src_attr(RTLIL::AttrObject *obj, const AstNode *ast)
return;
const auto &loc = ast->location;
if (!loc.begin.filename || loc.begin.filename->empty()) {
obj->set_src_attribute(&current_module->design->src_twines, ast->loc_string());
current_module->design->set_src_attribute(obj, ast->loc_string());
return;
}
// Split filename and per-location tail so the filename interns once
@ -1129,8 +1129,8 @@ void AST::set_src_attr(RTLIL::AttrObject *obj, const AstNode *ast)
loc.end.line, loc.end.column);
Twine::Id suffix_id = pool->intern_suffix(file_id, tail);
pool->release(file_id); // suffix internally holds a ref now
obj->set_src_id(pool, suffix_id);
pool->release(suffix_id); // set_src_id retained on obj's behalf
current_module->design->obj_set_src_id(obj, suffix_id);
pool->release(suffix_id); // obj_set_src_id retained on obj's behalf
}
static bool param_has_no_default(const AstNode* param) {

2
frontends/ast/genrtlil.cc
View file

@ -169,7 +169,7 @@ static void check_unique_id(RTLIL::Module *module, RTLIL::IdString id,
auto already_exists = [&](const RTLIL::AttrObject *existing, const char *existing_kind) {
std::string src;
if (module->design)
src = existing->get_src_attribute(&module->design->src_twines);
src = module->design->get_src_attribute(existing);
std::string location_str = "earlier";
if (!src.empty())
location_str = "at " + src;

16
frontends/json/jsonparse.cc
View file

@ -288,9 +288,9 @@ void json_parse_attr_param(dict<IdString, Const> &results, JsonNode *node)
}
// AttrObject-aware overload: extracts ID::src and routes it to the typed
// src_id_ field via set_src_attribute. Other keys still land in the
// attributes dict via the generic path.
void json_parse_attributes(TwinePool *pool, RTLIL::AttrObject *obj, JsonNode *node)
// meta-vector slot via Design::set_src_attribute. Other keys still land
// in the attributes dict via the generic path.
void json_parse_attributes(RTLIL::Design *design, RTLIL::AttrObject *obj, JsonNode *node)
{
if (node->type != 'D')
log_error("JSON attributes or parameters node is not a dictionary.\n");
@ -300,7 +300,7 @@ void json_parse_attributes(TwinePool *pool, RTLIL::AttrObject *obj, JsonNode *no
IdString key = RTLIL::escape_id(it.first.c_str());
Const value = json_parse_attr_param_value(it.second);
if (key == ID::src && (value.flags & RTLIL::CONST_FLAG_STRING))
obj->set_src_attribute(pool, value.decode_string());
design->set_src_attribute(obj, value.decode_string());
else
obj->attributes[key] = value;
}
@ -319,7 +319,7 @@ void json_import(Design *design, string &modname, JsonNode *node)
design->add(module);
if (node->data_dict.count("attributes"))
json_parse_attributes(&design->src_twines, module, node->data_dict.at("attributes"));
json_parse_attributes(design, module, node->data_dict.at("attributes"));
if (node->data_dict.count("parameter_default_values"))
json_parse_attr_param(module->parameter_default_values, node->data_dict.at("parameter_default_values"));
@ -502,7 +502,7 @@ void json_import(Design *design, string &modname, JsonNode *node)
}
if (net_node->data_dict.count("attributes"))
json_parse_attributes(&design->src_twines, wire, net_node->data_dict.at("attributes"));
json_parse_attributes(design, wire, net_node->data_dict.at("attributes"));
}
}
@ -583,7 +583,7 @@ void json_import(Design *design, string &modname, JsonNode *node)
}
if (cell_node->data_dict.count("attributes"))
json_parse_attributes(&design->src_twines, cell, cell_node->data_dict.at("attributes"));
json_parse_attributes(design, cell, cell_node->data_dict.at("attributes"));
if (cell_node->data_dict.count("parameters"))
json_parse_attr_param(cell->parameters, cell_node->data_dict.at("parameters"));
@ -631,7 +631,7 @@ void json_import(Design *design, string &modname, JsonNode *node)
}
if (memory_node->data_dict.count("attributes"))
json_parse_attributes(&design->src_twines, mem, memory_node->data_dict.at("attributes"));
json_parse_attributes(design, mem, memory_node->data_dict.at("attributes"));
module->memories[mem->name] = mem;
}

23
frontends/rtlil/rtlil_frontend.cc
View file

@ -452,7 +452,7 @@ struct RTLILFrontendWorker {
current_module->attributes = std::move(attrbuf);
} else {
design->add(current_module);
current_module->absorb_attrs(&design->src_twines, std::move(attrbuf));
current_module->absorb_attrs(std::move(attrbuf));
}
while (true)
@ -666,7 +666,7 @@ struct RTLILFrontendWorker {
error("Unexpected wire option: %s", error_token());
}
wire->absorb_attrs(&design->src_twines, std::move(attrbuf));
wire->absorb_attrs(std::move(attrbuf));
wire->width = width;
wire->upto = upto;
wire->start_offset = start_offset;
@ -681,7 +681,7 @@ struct RTLILFrontendWorker {
{
RTLIL::Memory *memory = new RTLIL::Memory;
memory->module = current_module;
memory->absorb_attrs(&design->src_twines, std::move(attrbuf));
memory->absorb_attrs(std::move(attrbuf));
int width = 1;
int start_offset = 0;
@ -749,7 +749,7 @@ struct RTLILFrontendWorker {
error("RTLIL error: redefinition of cell %s.", cell_name);
}
RTLIL::Cell *cell = current_module->addCell(cell_name, cell_type);
cell->absorb_attrs(&design->src_twines, std::move(attrbuf));
cell->absorb_attrs(std::move(attrbuf));
while (true)
{
@ -839,7 +839,7 @@ struct RTLILFrontendWorker {
{
RTLIL::SwitchRule *rule = new RTLIL::SwitchRule;
rule->signal = parse_sigspec();
rule->absorb_attrs(&design->src_twines, std::move(attrbuf));
rule->absorb_attrs(std::move(attrbuf));
switch_stack.back()->push_back(rule);
expect_eol();
@ -856,7 +856,7 @@ struct RTLILFrontendWorker {
expect_keyword("case");
RTLIL::CaseRule *case_rule = new RTLIL::CaseRule;
case_rule->absorb_attrs(&design->src_twines, std::move(attrbuf));
case_rule->absorb_attrs(std::move(attrbuf));
rule->cases.push_back(case_rule);
switch_stack.push_back(&case_rule->switches);
case_stack.push_back(case_rule);
@ -890,7 +890,7 @@ struct RTLILFrontendWorker {
error("RTLIL error: redefinition of process %s.", proc_name);
}
RTLIL::Process *proc = current_module->addProcess(std::move(proc_name));
proc->absorb_attrs(&design->src_twines, std::move(attrbuf));
proc->absorb_attrs(std::move(attrbuf));
switch_stack.clear();
switch_stack.push_back(&proc->root_case.switches);
@ -939,13 +939,18 @@ struct RTLILFrontendWorker {
break;
RTLIL::MemWriteAction act;
act.absorb_attrs(&design->src_twines, std::move(attrbuf));
act.module = current_module;
design->absorb_attrs(&act, std::move(attrbuf));
act.memid = parse_id();
act.address = parse_sigspec();
act.data = parse_sigspec();
act.enable = parse_sigspec();
act.priority_mask = parse_const();
rule->mem_write_actions.push_back(std::move(act));
rule->mem_write_actions.push_back(act);
// meta_idx_ is a weak ref — drop ours so the pushed copy
// in the vector is the sole holder. Process::~Process
// walks the tree to actually release.
act.meta_idx_ = RTLIL::AttrObject::NO_META;
expect_eol();
}
// The old parser allowed dangling attributes before a "sync" to carry through