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Code Activity
yosys/frontends
History
Emil J. Tywoniak d13dfc21f4 WIP
2026-06-10 14:54:48 +02:00
..
aiger rtlil: set Module::design before name at all construction sites 2026-06-10 14:54:39 +02:00
aiger2 Refactored uses of log_id() 2026-05-08 20:59:24 -07:00
ast WIP 2026-06-10 14:54:48 +02:00
blif rtlil: set Module::design before name at all construction sites 2026-06-10 14:54:39 +02:00
json rtlil: set Module::design before name at all construction sites 2026-06-10 14:54:39 +02:00
liberty WIP 2026-06-10 14:54:48 +02:00
rpc rtlil: fix masquerade 2026-06-10 14:54:45 +02:00
rtlil WIP 2026-06-10 14:54:48 +02:00
verific rtlil: set Module::design before name at all construction sites 2026-06-10 14:54:39 +02:00
verilog Support positional assignment patterns for unpacked arrays 2026-04-23 14:29:38 -07:00