mirror of
https://github.com/YosysHQ/yosys
synced 2026-03-07 13:54:54 +00:00
fixup! read_liberty: model clear_preset_variable correctly
This commit is contained in:
parent
39343f5f33
commit
85013f9ed3
1 changed files with 1 additions and 7 deletions
|
|
@ -213,7 +213,6 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node)
|
|||
bool clk_polarity = true, clear_polarity = true, preset_polarity = true;
|
||||
const std::string name = RTLIL::unescape_id(module->name);
|
||||
|
||||
bool clear_preset_reported = false;
|
||||
std::optional<char> clear_preset_var1;
|
||||
std::optional<char> clear_preset_var2;
|
||||
for (auto child : node->children) {
|
||||
|
|
@ -234,12 +233,6 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node)
|
|||
}
|
||||
|
||||
}
|
||||
if (clear_preset_var1 == 'X' || clear_preset_var2 == 'X') {
|
||||
if (!clear_preset_reported) {
|
||||
log_warning("FF cell %s has well-defined clear&preset behavior, but Yosys models it as undefined\n", name);
|
||||
clear_preset_reported = true;
|
||||
}
|
||||
}
|
||||
|
||||
if (clk_sig.size() == 0 || data_sig.size() == 0)
|
||||
log_error("FF cell %s has no next_state and/or clocked_on attribute.\n", name);
|
||||
|
|
@ -844,3 +837,4 @@ skip_cell:;
|
|||
|
||||
YOSYS_NAMESPACE_END
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue