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liberty: better twines
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parent
e451ceaf5d
commit
2255b3f523
1 changed files with 4 additions and 4 deletions
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@ -47,7 +47,7 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *&
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return *(expr++) == '0' ? RTLIL::State::S0 : RTLIL::State::S1;
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std::string id = RTLIL::escape_id(std::string(expr, id_len));
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TwineRef wire_ref = TwineSearch(&module->design->twines).find(id);
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TwineRef wire_ref = module->design->twines.find(id);
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RTLIL::Wire *w = module->wire(wire_ref);
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if (!w)
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log_error("Can't resolve wire name %s in %s.\n", RTLIL::unescape_id(id), module);
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@ -202,8 +202,8 @@ static void create_latch_ff_wires(RTLIL::Module *module, const LibertyAst *node)
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static std::pair<RTLIL::SigSpec, RTLIL::SigSpec> find_latch_ff_wires(RTLIL::Module *module, const LibertyAst *node)
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{
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TwineRef iq_ref = TwineSearch(&module->design->twines).find(RTLIL::escape_id(node->args.at(0)));
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TwineRef iqn_ref = TwineSearch(&module->design->twines).find(RTLIL::escape_id(node->args.at(1)));
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TwineRef iq_ref = module->design->twines.find(RTLIL::escape_id(node->args.at(0)));
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TwineRef iqn_ref = module->design->twines.find(RTLIL::escape_id(node->args.at(1)));
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auto* iq_wire = module->wire(iq_ref);
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auto* iqn_wire = module->wire(iqn_ref);
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log_assert(iq_wire && iqn_wire);
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@ -734,7 +734,7 @@ struct LibertyFrontend : public Frontend {
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if (flag_lib && dir->value == "internal")
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continue;
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TwineRef wire_ref = TwineSearch(&module->design->twines).find(RTLIL::escape_id(node->args.at(0)));
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TwineRef wire_ref = module->design->twines.find(RTLIL::escape_id(node->args.at(0)));
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RTLIL::Wire *wire = module->wire(wire_ref);
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log_assert(wire);
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