mirror of
https://github.com/YosysHQ/yosys
synced 2026-07-20 06:05:50 +00:00
WIP
This commit is contained in:
Emil J. Tywoniak
parent
015ab4e45b
commit
f592f2f3af
203 changed files with 4575 additions and 4481 deletions
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@ -130,7 +130,7 @@ struct ConstEvalAig
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sig2deps[output].insert(output);
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RTLIL::Cell *cell = sig2driver.at(output);
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RTLIL::SigBit sig_a = cell->getPort(ID::A);
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RTLIL::SigBit sig_a = cell->getPort(TW::A);
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sig2deps[sig_a].reserve(sig2deps[sig_a].size() + sig2deps[output].size()); // Reserve so that any invalidation
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// that may occur does so here, and
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// not mid insertion (below)
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@ -139,7 +139,7 @@ struct ConstEvalAig
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compute_deps(sig_a, inputs);
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if (cell->type == ID($_AND_)) {
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RTLIL::SigSpec sig_b = cell->getPort(ID::B);
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RTLIL::SigSpec sig_b = cell->getPort(TW::B);
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sig2deps[sig_b].reserve(sig2deps[sig_b].size() + sig2deps[output].size()); // Reserve so that any invalidation
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// that may occur does so here, and
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// not mid insertion (below)
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@ -155,11 +155,11 @@ struct ConstEvalAig
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bool eval(RTLIL::Cell *cell)
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{
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RTLIL::SigBit sig_y = cell->getPort(ID::Y);
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RTLIL::SigBit sig_y = cell->getPort(TW::Y);
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if (values_map.count(sig_y))
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return true;
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RTLIL::SigBit sig_a = cell->getPort(ID::A);
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RTLIL::SigBit sig_a = cell->getPort(TW::A);
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if (!eval(sig_a))
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return false;
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@ -175,7 +175,7 @@ struct ConstEvalAig
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}
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{
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RTLIL::SigBit sig_b = cell->getPort(ID::B);
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RTLIL::SigBit sig_b = cell->getPort(TW::B);
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if (!eval(sig_b))
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return false;
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if (sig_b == State::S0) {
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@ -978,7 +978,7 @@ void AigerReader::post_process()
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for (auto cell : module->cells().to_vector()) {
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if (cell->type != ID($lut)) continue;
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auto y_port = cell->getPort(ID::Y).as_bit();
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auto y_port = cell->getPort(TW::Y).as_bit();
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if (y_port.wire->width == 1)
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module->rename(cell, stringf("$lut%s", y_port.wire->name));
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else
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@ -62,10 +62,10 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, IdString type, int result_width
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cell->parameters[ID::A_SIGNED] = RTLIL::Const(that->children[0]->is_signed);
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cell->parameters[ID::A_WIDTH] = RTLIL::Const(arg.size());
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cell->setPort(ID::A, arg);
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cell->setPort(TW::A, arg);
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cell->parameters[ID::Y_WIDTH] = result_width;
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cell->setPort(ID::Y, wire);
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cell->setPort(TW::Y, wire);
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return wire;
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}
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@ -94,10 +94,10 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
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cell->parameters[ID::A_SIGNED] = RTLIL::Const(is_signed);
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cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig.size());
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cell->setPort(ID::A, sig);
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cell->setPort(TW::A, sig);
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cell->parameters[ID::Y_WIDTH] = width;
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cell->setPort(ID::Y, wire);
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cell->setPort(TW::Y, wire);
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sig = wire;
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}
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@ -124,11 +124,11 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, IdString type, int result_width
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cell->parameters[ID::A_WIDTH] = RTLIL::Const(left.size());
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cell->parameters[ID::B_WIDTH] = RTLIL::Const(right.size());
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cell->setPort(ID::A, left);
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cell->setPort(ID::B, right);
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cell->setPort(TW::A, left);
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cell->setPort(TW::B, right);
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cell->parameters[ID::Y_WIDTH] = result_width;
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cell->setPort(ID::Y, wire);
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cell->setPort(TW::Y, wire);
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return wire;
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}
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@ -155,10 +155,10 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
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cell->parameters[ID::WIDTH] = RTLIL::Const(left.size());
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cell->setPort(ID::A, right);
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cell->setPort(ID::B, left);
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cell->setPort(ID::S, cond);
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cell->setPort(ID::Y, wire);
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cell->setPort(TW::A, right);
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cell->setPort(TW::B, left);
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cell->setPort(TW::S, cond);
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cell->setPort(TW::Y, wire);
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return wire;
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}
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@ -842,8 +842,8 @@ struct AST_INTERNAL::ProcessGenerator
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cell->setParam(ID::TRG_ENABLE, (always->type == AST_INITIAL) || !triggers.empty());
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cell->setParam(ID::TRG_POLARITY, polarity);
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cell->setParam(ID::PRIORITY, --last_effect_priority);
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cell->setPort(ID::TRG, triggers);
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cell->setPort(ID::EN, en);
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cell->setPort(TW::TRG, triggers);
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cell->setPort(TW::EN, en);
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int default_base = 10;
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if (ast->str.back() == 'b')
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@ -947,9 +947,9 @@ struct AST_INTERNAL::ProcessGenerator
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cell->setParam(ID::TRG_ENABLE, (always->type == AST_INITIAL) || !triggers.empty());
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cell->setParam(ID::TRG_POLARITY, polarity);
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cell->setParam(ID::PRIORITY, --last_effect_priority);
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cell->setPort(ID::TRG, triggers);
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cell->setPort(ID::EN, en);
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cell->setPort(ID::A, check);
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cell->setPort(TW::TRG, triggers);
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cell->setPort(TW::EN, en);
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cell->setPort(TW::A, check);
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// No message is emitted to ensure Verilog code roundtrips correctly.
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Fmt fmt;
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@ -2058,10 +2058,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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RTLIL::SigSpec addr_sig = children[0]->genRTLIL();
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cell->setPort(ID::CLK, RTLIL::SigSpec(RTLIL::State::Sx, 1));
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cell->setPort(ID::EN, RTLIL::SigSpec(RTLIL::State::Sx, 1));
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cell->setPort(ID::ADDR, addr_sig);
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cell->setPort(ID::DATA, RTLIL::SigSpec(wire));
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cell->setPort(TW::CLK, RTLIL::SigSpec(RTLIL::State::Sx, 1));
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cell->setPort(TW::EN, RTLIL::SigSpec(RTLIL::State::Sx, 1));
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cell->setPort(TW::ADDR, addr_sig);
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cell->setPort(TW::DATA, RTLIL::SigSpec(wire));
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cell->parameters[ID::MEMID] = RTLIL::Const(str);
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cell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr_sig));
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@ -2098,9 +2098,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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SigSpec addr_sig = children[0]->genRTLIL();
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cell->setPort(ID::ADDR, addr_sig);
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cell->setPort(ID::DATA, children[1]->genWidthRTLIL(current_module->memories[str]->width * num_words, true));
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cell->setPort(ID::EN, en_sig);
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cell->setPort(TW::ADDR, addr_sig);
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cell->setPort(TW::DATA, children[1]->genWidthRTLIL(current_module->memories[str]->width * num_words, true));
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cell->setPort(TW::EN, en_sig);
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cell->parameters[ID::MEMID] = RTLIL::Const(str);
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cell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr_sig));
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@ -2147,9 +2147,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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cell->parameters[ID::TRG_ENABLE] = 0;
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cell->parameters[ID::TRG_POLARITY] = 0;
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cell->parameters[ID::PRIORITY] = 0;
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cell->setPort(ID::TRG, RTLIL::SigSpec());
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cell->setPort(ID::EN, RTLIL::S1);
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cell->setPort(ID::A, check);
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cell->setPort(TW::TRG, RTLIL::SigSpec());
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cell->setPort(TW::EN, RTLIL::S1);
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cell->setPort(TW::A, check);
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// No message is emitted to ensure Verilog code roundtrips correctly.
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Fmt fmt;
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@ -2262,8 +2262,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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cell->attributes[attr.first] = attr.second->asAttrConst();
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}
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if (cell->type == ID($specify2)) {
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int src_width = GetSize(cell->getPort(ID::SRC));
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int dst_width = GetSize(cell->getPort(ID::DST));
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int src_width = GetSize(cell->getPort(TW::SRC));
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int dst_width = GetSize(cell->getPort(TW::DST));
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bool full = cell->getParam(ID::FULL).as_bool();
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if (!full && src_width != dst_width)
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input_error("Parallel specify SRC width does not match DST width.\n");
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@ -2271,17 +2271,17 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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cell->setParam(ID::DST_WIDTH, Const(dst_width));
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}
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else if (cell->type == ID($specify3)) {
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int dat_width = GetSize(cell->getPort(ID::DAT));
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int dst_width = GetSize(cell->getPort(ID::DST));
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int dat_width = GetSize(cell->getPort(TW::DAT));
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int dst_width = GetSize(cell->getPort(TW::DST));
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if (dat_width != dst_width)
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input_error("Specify DAT width does not match DST width.\n");
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int src_width = GetSize(cell->getPort(ID::SRC));
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int src_width = GetSize(cell->getPort(TW::SRC));
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cell->setParam(ID::SRC_WIDTH, Const(src_width));
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cell->setParam(ID::DST_WIDTH, Const(dst_width));
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}
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else if (cell->type == ID($specrule)) {
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int src_width = GetSize(cell->getPort(ID::SRC));
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int dst_width = GetSize(cell->getPort(ID::DST));
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int src_width = GetSize(cell->getPort(TW::SRC));
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int dst_width = GetSize(cell->getPort(TW::DST));
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cell->setParam(ID::SRC_WIDTH, Const(src_width));
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cell->setParam(ID::DST_WIDTH, Const(dst_width));
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}
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@ -2370,7 +2370,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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Wire *wire = current_module->addWire(myid + "_wire", width);
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set_src_attr(wire, this);
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cell->setPort(ID::Y, wire);
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cell->setPort(TW::Y, wire);
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is_signed = sign_hint;
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return SigSpec(wire);
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@ -1479,7 +1479,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
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continue;
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// determine the full name of port this argument is connected to
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RTLIL::IdString port_name;
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TwineRef port_name;
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if (child->str.size())
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port_name = child->str;
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else {
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@ -226,7 +226,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
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for (auto cell : module->cells())
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if (cell->type == ID($lut) && cell->getParam(ID::LUT) == buffer_lut) {
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module->connect(cell->getPort(ID::Y), cell->getPort(ID::A));
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module->connect(cell->getPort(TW::Y), cell->getPort(TW::A));
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remove_cells.push_back(cell);
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}
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@ -376,9 +376,9 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
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if (dff_name.empty()) {
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cell = module->addFfGate(NEW_ID, blif_wire(d), blif_wire(q));
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} else {
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cell = module->addCell(NEW_ID, dff_name);
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cell->setPort(ID::D, blif_wire(d));
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cell->setPort(ID::Q, blif_wire(q));
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cell = module->addCell(NEW_TWINE, dff_name);
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cell->setPort(TW::D, blif_wire(d));
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cell->setPort(TW::Q, blif_wire(q));
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}
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}
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@ -395,7 +395,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
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goto error;
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IdString celltype = RTLIL::escape_id(p);
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RTLIL::Cell *cell = module->addCell(NEW_ID, celltype);
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RTLIL::Cell *cell = module->addCell(NEW_TWINE, celltype);
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RTLIL::Module *cell_mod = design->module(celltype);
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dict<RTLIL::IdString, dict<int, SigBit>> cell_wideports_cache;
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@ -442,7 +442,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
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if (it.second.count(idx))
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sig.append(it.second.at(idx));
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else
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sig.append(module->addWire(NEW_ID));
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sig.append(module->addWire(NEW_TWINE));
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}
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cell->setPort(it.first, sig);
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@ -539,12 +539,12 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
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if (sop_mode)
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{
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sopcell = module->addCell(NEW_ID, ID($sop));
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sopcell = module->addCell(NEW_TWINE, ID($sop));
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sopcell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size());
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sopcell->parameters[ID::DEPTH] = 0;
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sopcell->parameters[ID::TABLE] = RTLIL::Const();
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sopcell->setPort(ID::A, input_sig);
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sopcell->setPort(ID::Y, output_sig);
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sopcell->setPort(TW::A, input_sig);
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sopcell->setPort(TW::Y, output_sig);
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sopmode = -1;
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lastcell = sopcell;
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}
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@ -555,11 +555,11 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
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}
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else
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{
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RTLIL::Cell *cell = module->addCell(NEW_ID, ID($lut));
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RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($lut));
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cell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size());
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cell->parameters[ID::LUT] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size());
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cell->setPort(ID::A, input_sig);
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cell->setPort(ID::Y, output_sig);
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cell->setPort(TW::A, input_sig);
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cell->setPort(TW::Y, output_sig);
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lutptr = &cell->parameters.at(ID::LUT);
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lut_default_state = RTLIL::State::Sx;
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lastcell = cell;
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@ -607,10 +607,10 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
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if (sopmode == -1) {
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sopmode = (*output == '1');
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if (!sopmode) {
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SigSpec outnet = sopcell->getPort(ID::Y);
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SigSpec tempnet = module->addWire(NEW_ID);
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SigSpec outnet = sopcell->getPort(TW::Y);
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SigSpec tempnet = module->addWire(NEW_TWINE);
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module->addNotGate(NEW_ID, tempnet, outnet);
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sopcell->setPort(ID::Y, tempnet);
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sopcell->setPort(TW::Y, tempnet);
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}
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} else
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log_assert(sopmode == (*output == '1'));
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@ -572,7 +572,7 @@ void json_import(Design *design, string &modname, JsonNode *node)
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if (bitval_node->type == 'N') {
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int bitidx = bitval_node->data_number;
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if (signal_bits.count(bitidx) == 0)
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signal_bits[bitidx] = module->addWire(NEW_ID);
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signal_bits[bitidx] = module->addWire(NEW_TWINE);
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sig.append(signal_bits.at(bitidx));
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} else
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log_error("JSON cells node '%s' connection '%s' has invalid bit value on bit %d.\n",
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@ -185,12 +185,12 @@ static RTLIL::SigSpec create_tristate(RTLIL::Module *module, RTLIL::SigSpec func
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{
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RTLIL::SigSpec three_state = parse_func_expr(module, three_state_expr);
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RTLIL::Cell *cell = module->addCell(NEW_ID, ID($tribuf));
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RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($tribuf));
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cell->setParam(ID::WIDTH, GetSize(func));
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cell->setPort(ID::A, func);
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cell->setPort(ID::EN, module->NotGate(NEW_ID, three_state));
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cell->setPort(ID::Y, module->addWire(NEW_ID));
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return cell->getPort(ID::Y);
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cell->setPort(TW::A, func);
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cell->setPort(TW::EN, module->NotGate(NEW_ID, three_state));
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cell->setPort(TW::Y, module->addWire(NEW_TWINE));
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return cell->getPort(TW::Y);
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}
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static void create_latch_ff_wires(RTLIL::Module *module, const LibertyAst *node)
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@ -243,18 +243,18 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node)
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rerun_invert_rollback = false;
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for (auto &it : module->cells_) {
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if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == clk_sig) {
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clk_sig = it.second->getPort(ID::A);
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if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == clk_sig) {
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clk_sig = it.second->getPort(TW::A);
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clk_polarity = !clk_polarity;
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rerun_invert_rollback = true;
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}
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if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == clear_sig) {
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clear_sig = it.second->getPort(ID::A);
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if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == clear_sig) {
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clear_sig = it.second->getPort(TW::A);
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clear_polarity = !clear_polarity;
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rerun_invert_rollback = true;
|
||||
}
|
||||
if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == preset_sig) {
|
||||
preset_sig = it.second->getPort(ID::A);
|
||||
if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == preset_sig) {
|
||||
preset_sig = it.second->getPort(TW::A);
|
||||
preset_polarity = !preset_polarity;
|
||||
rerun_invert_rollback = true;
|
||||
}
|
||||
|
|
@ -264,14 +264,14 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node)
|
|||
for (auto& [out_sig, cp_var, neg] : {tuple{iq_sig, clear_preset_var1, false}, {iqn_sig, clear_preset_var2, true}}) {
|
||||
SigSpec q_sig = out_sig;
|
||||
if (neg) {
|
||||
q_sig = module->addWire(NEW_ID, out_sig.as_wire());
|
||||
q_sig = module->addWire(NEW_TWINE, out_sig.as_wire());
|
||||
module->addNotGate(NEW_ID, q_sig, out_sig);
|
||||
}
|
||||
|
||||
RTLIL::Cell* cell = module->addCell(NEW_ID, "");
|
||||
cell->setPort(ID::D, data_sig);
|
||||
cell->setPort(ID::Q, q_sig);
|
||||
cell->setPort(ID::C, clk_sig);
|
||||
RTLIL::Cell* cell = module->addCell(NEW_TWINE, "");
|
||||
cell->setPort(TW::D, data_sig);
|
||||
cell->setPort(TW::Q, q_sig);
|
||||
cell->setPort(TW::C, clk_sig);
|
||||
|
||||
if (clear_sig.size() == 0 && preset_sig.size() == 0) {
|
||||
cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N');
|
||||
|
|
@ -279,12 +279,12 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node)
|
|||
|
||||
if (clear_sig.size() == 1 && preset_sig.size() == 0) {
|
||||
cell->type = stringf("$_DFF_%c%c0_", clk_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N');
|
||||
cell->setPort(ID::R, clear_sig);
|
||||
cell->setPort(TW::R, clear_sig);
|
||||
}
|
||||
|
||||
if (clear_sig.size() == 0 && preset_sig.size() == 1) {
|
||||
cell->type = stringf("$_DFF_%c%c1_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N');
|
||||
cell->setPort(ID::R, preset_sig);
|
||||
cell->setPort(TW::R, preset_sig);
|
||||
}
|
||||
|
||||
if (clear_sig.size() == 1 && preset_sig.size() == 1) {
|
||||
|
|
@ -313,8 +313,8 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node)
|
|||
log_debug("cell %s variable %d undef c&p behavior\n", name, (int)neg + 1);
|
||||
}
|
||||
|
||||
cell->setPort(ID::S, s_sig);
|
||||
cell->setPort(ID::R, r_sig);
|
||||
cell->setPort(TW::S, s_sig);
|
||||
cell->setPort(TW::R, r_sig);
|
||||
}
|
||||
|
||||
log_assert(!cell->type.empty());
|
||||
|
|
@ -352,27 +352,27 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
|
|||
rerun_invert_rollback = false;
|
||||
|
||||
for (auto &it : module->cells_) {
|
||||
if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == enable_sig) {
|
||||
enable_sig = it.second->getPort(ID::A);
|
||||
if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == enable_sig) {
|
||||
enable_sig = it.second->getPort(TW::A);
|
||||
enable_polarity = !enable_polarity;
|
||||
rerun_invert_rollback = true;
|
||||
}
|
||||
if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == clear_sig) {
|
||||
clear_sig = it.second->getPort(ID::A);
|
||||
if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == clear_sig) {
|
||||
clear_sig = it.second->getPort(TW::A);
|
||||
clear_polarity = !clear_polarity;
|
||||
rerun_invert_rollback = true;
|
||||
}
|
||||
if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == preset_sig) {
|
||||
preset_sig = it.second->getPort(ID::A);
|
||||
if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == preset_sig) {
|
||||
preset_sig = it.second->getPort(TW::A);
|
||||
preset_polarity = !preset_polarity;
|
||||
rerun_invert_rollback = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_NOT_));
|
||||
cell->setPort(ID::A, iq_sig);
|
||||
cell->setPort(ID::Y, iqn_sig);
|
||||
RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($_NOT_));
|
||||
cell->setPort(TW::A, iq_sig);
|
||||
cell->setPort(TW::Y, iqn_sig);
|
||||
|
||||
if (clear_sig.size() == 1)
|
||||
{
|
||||
|
|
@ -381,25 +381,25 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
|
|||
|
||||
if (clear_polarity == true || clear_polarity != enable_polarity)
|
||||
{
|
||||
RTLIL::Cell *inv = module->addCell(NEW_ID, ID($_NOT_));
|
||||
inv->setPort(ID::A, clear_sig);
|
||||
inv->setPort(ID::Y, module->addWire(NEW_ID));
|
||||
RTLIL::Cell *inv = module->addCell(NEW_TWINE, ID($_NOT_));
|
||||
inv->setPort(TW::A, clear_sig);
|
||||
inv->setPort(TW::Y, module->addWire(NEW_TWINE));
|
||||
|
||||
if (clear_polarity == true)
|
||||
clear_negative = inv->getPort(ID::Y);
|
||||
clear_negative = inv->getPort(TW::Y);
|
||||
if (clear_polarity != enable_polarity)
|
||||
clear_enable = inv->getPort(ID::Y);
|
||||
clear_enable = inv->getPort(TW::Y);
|
||||
}
|
||||
|
||||
RTLIL::Cell *data_gate = module->addCell(NEW_ID, ID($_AND_));
|
||||
data_gate->setPort(ID::A, data_sig);
|
||||
data_gate->setPort(ID::B, clear_negative);
|
||||
data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
|
||||
RTLIL::Cell *data_gate = module->addCell(NEW_TWINE, ID($_AND_));
|
||||
data_gate->setPort(TW::A, data_sig);
|
||||
data_gate->setPort(TW::B, clear_negative);
|
||||
data_gate->setPort(TW::Y, data_sig = module->addWire(NEW_TWINE));
|
||||
|
||||
RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? ID($_OR_) : ID($_AND_));
|
||||
enable_gate->setPort(ID::A, enable_sig);
|
||||
enable_gate->setPort(ID::B, clear_enable);
|
||||
enable_gate->setPort(ID::Y, enable_sig = module->addWire(NEW_ID));
|
||||
RTLIL::Cell *enable_gate = module->addCell(NEW_TWINE, enable_polarity ? ID($_OR_) : ID($_AND_));
|
||||
enable_gate->setPort(TW::A, enable_sig);
|
||||
enable_gate->setPort(TW::B, clear_enable);
|
||||
enable_gate->setPort(TW::Y, enable_sig = module->addWire(NEW_TWINE));
|
||||
}
|
||||
|
||||
if (preset_sig.size() == 1)
|
||||
|
|
@ -409,31 +409,31 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
|
|||
|
||||
if (preset_polarity == false || preset_polarity != enable_polarity)
|
||||
{
|
||||
RTLIL::Cell *inv = module->addCell(NEW_ID, ID($_NOT_));
|
||||
inv->setPort(ID::A, preset_sig);
|
||||
inv->setPort(ID::Y, module->addWire(NEW_ID));
|
||||
RTLIL::Cell *inv = module->addCell(NEW_TWINE, ID($_NOT_));
|
||||
inv->setPort(TW::A, preset_sig);
|
||||
inv->setPort(TW::Y, module->addWire(NEW_TWINE));
|
||||
|
||||
if (preset_polarity == false)
|
||||
preset_positive = inv->getPort(ID::Y);
|
||||
preset_positive = inv->getPort(TW::Y);
|
||||
if (preset_polarity != enable_polarity)
|
||||
preset_enable = inv->getPort(ID::Y);
|
||||
preset_enable = inv->getPort(TW::Y);
|
||||
}
|
||||
|
||||
RTLIL::Cell *data_gate = module->addCell(NEW_ID, ID($_OR_));
|
||||
data_gate->setPort(ID::A, data_sig);
|
||||
data_gate->setPort(ID::B, preset_positive);
|
||||
data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
|
||||
RTLIL::Cell *data_gate = module->addCell(NEW_TWINE, ID($_OR_));
|
||||
data_gate->setPort(TW::A, data_sig);
|
||||
data_gate->setPort(TW::B, preset_positive);
|
||||
data_gate->setPort(TW::Y, data_sig = module->addWire(NEW_TWINE));
|
||||
|
||||
RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? ID($_OR_) : ID($_AND_));
|
||||
enable_gate->setPort(ID::A, enable_sig);
|
||||
enable_gate->setPort(ID::B, preset_enable);
|
||||
enable_gate->setPort(ID::Y, enable_sig = module->addWire(NEW_ID));
|
||||
RTLIL::Cell *enable_gate = module->addCell(NEW_TWINE, enable_polarity ? ID($_OR_) : ID($_AND_));
|
||||
enable_gate->setPort(TW::A, enable_sig);
|
||||
enable_gate->setPort(TW::B, preset_enable);
|
||||
enable_gate->setPort(TW::Y, enable_sig = module->addWire(NEW_TWINE));
|
||||
}
|
||||
|
||||
cell = module->addCell(NEW_ID, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N'));
|
||||
cell->setPort(ID::D, data_sig);
|
||||
cell->setPort(ID::Q, iq_sig);
|
||||
cell->setPort(ID::E, enable_sig);
|
||||
cell = module->addCell(NEW_TWINE, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N'));
|
||||
cell->setPort(TW::D, data_sig);
|
||||
cell->setPort(TW::Q, iq_sig);
|
||||
cell->setPort(TW::E, enable_sig);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
|
@ -793,7 +793,7 @@ struct LibertyFrontend : public Frontend {
|
|||
if (wi->port_input) {
|
||||
for (auto wo : module->wires())
|
||||
if (wo->port_output) {
|
||||
RTLIL::Cell *spec = module->addCell(NEW_ID, ID($specify2));
|
||||
RTLIL::Cell *spec = module->addCell(NEW_TWINE, ID($specify2));
|
||||
spec->setParam(ID::SRC_WIDTH, wi->width);
|
||||
spec->setParam(ID::DST_WIDTH, wo->width);
|
||||
spec->setParam(ID::T_FALL_MAX, 1000);
|
||||
|
|
@ -805,9 +805,9 @@ struct LibertyFrontend : public Frontend {
|
|||
spec->setParam(ID::SRC_DST_POL, false);
|
||||
spec->setParam(ID::SRC_DST_PEN, false);
|
||||
spec->setParam(ID::FULL, true);
|
||||
spec->setPort(ID::EN, Const(1, 1));
|
||||
spec->setPort(ID::SRC, wi);
|
||||
spec->setPort(ID::DST, wo);
|
||||
spec->setPort(TW::EN, Const(1, 1));
|
||||
spec->setPort(TW::SRC, wi);
|
||||
spec->setPort(TW::DST, wo);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -445,7 +445,7 @@ struct RTLILFrontendWorker {
|
|||
|
||||
current_module = new RTLIL::Module;
|
||||
current_module->design = design;
|
||||
current_module->meta_->name_id = module_name;
|
||||
current_module->meta_->name = module_name;
|
||||
if (delete_current_module) {
|
||||
// Module is about to be discarded — drop its src attribute
|
||||
// rather than push it into a pool we'll never reach.
|
||||
|
|
@ -706,7 +706,7 @@ struct RTLILFrontendWorker {
|
|||
expect_eol();
|
||||
}
|
||||
|
||||
void legalize_width_parameter(RTLIL::Cell *cell, RTLIL::IdString port_name)
|
||||
void legalize_width_parameter(RTLIL::Cell *cell, TwineRef port_name)
|
||||
{
|
||||
std::string width_param_name = port_name.str() + "_WIDTH";
|
||||
if (cell->parameters.count(width_param_name) == 0)
|
||||
|
|
@ -763,7 +763,7 @@ struct RTLILFrontendWorker {
|
|||
cell->parameters.insert({std::move(param_name), std::move(val)});
|
||||
expect_eol();
|
||||
} else if (try_parse_keyword("connect")) {
|
||||
RTLIL::IdString port_name = parse_id();
|
||||
TwineRef port_name = parse_id();
|
||||
if (cell->hasPort(port_name)) {
|
||||
if (flag_legalize)
|
||||
log("Legalizing redefinition of cell port %s.", port_name);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue