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This commit is contained in:
Emil J. Tywoniak 2026-06-12 16:25:07 +02:00
parent c3ffbf6fae
commit d22805bd47
65 changed files with 739 additions and 718 deletions
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10
frontends/aiger/aigerparse.cc
View file

@ -837,7 +837,7 @@ void AigerReader::post_process()
wire->port_input = false;
module->connect(wire, existing);
}
log_debug(" -> %s\n", design->twines.unescaped_str(escaped_s));
log_debug(" -> %s\n", log_id(escaped_s));
}
else {
RTLIL::IdString indexed_name = stringf("%s[%d]", escaped_s, index);
@ -848,7 +848,7 @@ void AigerReader::post_process()
module->connect(wire, existing);
wire->port_input = false;
}
log_debug(" -> %s\n", design->twines.unescaped_str(indexed_name));
log_debug(" -> %s\n", log_id(indexed_name));
}
if (wideports && !existing) {
@ -884,7 +884,7 @@ void AigerReader::post_process()
module->connect(wire, existing);
wire = existing;
}
log_debug(" -> %s\n", design->twines.unescaped_str(escaped_s));
log_debug(" -> %s\n", log_id(escaped_s));
}
else {
RTLIL::IdString indexed_name = stringf("%s[%d]", escaped_s, index);
@ -896,7 +896,7 @@ void AigerReader::post_process()
existing->port_output = true;
module->connect(wire, existing);
}
log_debug(" -> %s\n", design->twines.unescaped_str(indexed_name));
log_debug(" -> %s\n", log_id(indexed_name));
}
if (wideports && !existing) {
@ -914,7 +914,7 @@ void AigerReader::post_process()
else if (type == "box") {
RTLIL::Cell* cell = module->cell(design->twines.lookup(stringf("$box%d", variable)));
if (!cell)
log_debug("Box %d (%s) no longer exists.\n", variable, design->twines.unescaped_str(escaped_s));
log_debug("Box %d (%s) no longer exists.\n", variable, log_id(escaped_s));
else
module->rename(cell, design->twines.add(Twine{escaped_s.str()}));
}

4
frontends/ast/genrtlil.cc
View file

@ -2203,10 +2203,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
const auto* value = child->children[0].get();
if (value->type == AST_REALVALUE)
log_file_warning(*location.begin.filename, location.begin.line, "Replacing floating point parameter %s.%s = %f with string.\n",
cell, design->twines.unescaped_str(paraname), value->realvalue);
cell, log_id(paraname), value->realvalue);
else if (value->type != AST_CONSTANT)
input_error("Parameter %s.%s with non-constant value!\n",
cell, design->twines.unescaped_str(paraname));
cell, log_id(paraname));
cell->parameters[paraname] = value->asParaConst();
continue;
}

9
frontends/rtlil/rtlil_frontend.cc
View file

@ -341,7 +341,7 @@ struct RTLILFrontendWorker {
error("No wires found for legalization");
int hash = hash_ops<RTLIL::IdString>::hash(id).yield();
RTLIL::Wire *wire = current_module->wire_at(abs(hash % wires_size));
log("Legalizing wire `%s' to `%s'.\n", design->twines.unescaped_str(id), design->twines.unescaped_str(wire->name));
log("Legalizing wire `%s' to `%s'.\n", log_id(id), design->twines.unescaped_str(wire->name.ref()));
return wire;
}
@ -365,8 +365,11 @@ struct RTLILFrontendWorker {
if (wire == nullptr) {
if (flag_legalize)
wire = legalize_wire(*id);
else
else {
// for (auto wire : current_module->wires())
// design->twines.dump(wire->meta_->name);
error("Wire `%s' not found.", *id);
}
}
sig = RTLIL::SigSpec(wire);
} else {
@ -423,7 +426,7 @@ struct RTLILFrontendWorker {
void parse_module()
{
TwineRef module_name = design->twines.lookup(parse_id());
TwineRef module_name = design->twines.add(parse_id());
expect_eol();
bool delete_current_module = false;