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Code Activity
yosys/frontends
History
Emil J. Tywoniak ca632e82c4 rtlil: set Module* on inner-process AttrObjects at construction
2026-06-10 14:54:12 +02:00
..
aiger signorm: disable in passes that use swap_names 2026-05-22 18:37:58 +02:00
aiger2 Refactored uses of log_id() 2026-05-08 20:59:24 -07:00
ast rtlil: set Module* on inner-process AttrObjects at construction 2026-06-10 14:54:12 +02:00
blif Refactored uses of log_id() 2026-05-08 20:59:24 -07:00
json rtlil: evacuate src_id_ from AttrObject to per-Design meta vector 2026-06-10 14:54:05 +02:00
liberty Convert RTLIL::unescape_id of IdString to unescape() 2026-05-16 19:49:45 +02:00
rpc Refactored uses of log_id() 2026-05-08 20:59:24 -07:00
rtlil rtlil: set Module* on inner-process AttrObjects at construction 2026-06-10 14:54:12 +02:00
verific rtlil: set Module* on inner-process AttrObjects at construction 2026-06-10 14:54:12 +02:00
verilog Support positional assignment patterns for unpacked arrays 2026-04-23 14:29:38 -07:00