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Code Activity
15817 commits 122 branches 59 tags 72 MiB
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2160 commits

Author SHA1 Message Date
Eddie Hung
6274f0b075 opt_expr: add failing $xnor test 2020-03-20 14:38:50 -07:00
David Shah
fa77fb857b Add test for abc9+mince issue 
Signed-off-by: David Shah <dave@ds0.me>
 2020-03-20 20:35:28 +00:00
Eddie Hung
317c18fc6f Simplify breaking tests/arch/*/fsm.ys tests 2020-03-20 11:25:17 -07:00
Eddie Hung
81ca776ea4 opt_expr: add $xor/$xnor/$_XOR_/$_XNOR_ tests 2020-03-19 16:59:11 -07:00
Eddie Hung
5e2562f1a2 opt_expr: add $alu tests 2020-03-19 14:57:10 -07:00
Marcin Kościelnicki
e91368a5f4 fsm_extract: Initialize celltypes with full design. 
Fixes #1781.
 2020-03-19 18:51:21 +01:00
N. Engelhardt
e03f725ef2
Merge pull request #1774 from boqwxp/exec 
Add `exec` command to allow running shell commands from inside Yosys scripts
 2020-03-19 13:14:43 +01:00
N. Engelhardt
644deb708d fix argument order for macOS compatibility 2020-03-18 15:11:49 +01:00
Eddie Hung
9f30d7f843 opt_merge: speedup 2020-03-16 12:43:54 -07:00
Alberto Gonzalez
a09b260c01
Add test for exec command. 2020-03-16 07:52:58 +00:00
Miodrag Milanović
569e834df2
Merge pull request #1759 from zeldin/constant_with_comment_redux 
refixed parsing of constant with comment between size and value
 2020-03-14 13:34:59 +02:00
Marcus Comstedt
dd562f29e7 Add regression tests for new handling of comments in constants 2020-03-14 11:41:09 +01:00
Miodrag Milanović
faf4ee69de
Merge pull request #1754 from boqwxp/precise_locations 
Set AST node source location in more parser rules.
 2020-03-14 11:18:39 +02:00
Miodrag Milanovic
5b73e7c63a Added back tests for logger 2020-03-13 15:00:18 +01:00
Eddie Hung
3ada82639f verilog: add test 2020-03-11 06:51:03 -07:00
David Shah
ddcd87b577
Merge pull request #1721 from YosysHQ/dave/tribuf-unused 
deminout: Don't demote inouts with unused bits
 2020-03-10 13:51:40 +00:00
Claire Wolf
a7cc4673c3 Fix partsel expr bit width handling and add test case 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-03-08 16:12:12 +01:00
N. Engelhardt
88494e81f5 rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors 2020-03-06 15:29:01 +01:00
Eddie Hung
3c2e910bb3 tests: extend tests/arch/run-tests.sh for defines 2020-03-05 08:08:32 -08:00
David Shah
5cae9c6e16 deminout: Don't demote inouts with unused bits 
Signed-off-by: David Shah <dave@ds0.me>
 2020-03-04 18:44:38 +00:00
Claire Wolf
b597f85b13
Merge pull request #1718 from boqwxp/precise_locations 
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
 2020-03-03 08:38:32 -08:00
Claire Wolf
879124333f
Merge pull request #1519 from YosysHQ/eddie/submod_po 
submod: several bugfixes
 2020-03-03 08:19:06 -08:00
Marcelina Kościelnicka
968956badb
iopadmap: Look harder for already-present buffers. (#1731) 
iopadmap: Look harder for already-present buffers.

Fixes #1720.
 2020-03-02 21:40:09 +01:00
Eddie Hung
4f889b2f57
Merge pull request #1724 from YosysHQ/eddie/abc9_specify 
abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
 2020-03-02 12:32:27 -08:00
Eddie Hung
5bba9c3640 ast: fixes #1710; do not generate RTLIL for unreachable ternary 2020-02-27 16:55:55 -08:00
Eddie Hung
a179d918ec Revert "Fix tests/arch/xilinx/fsm.ys to count flops only" 
This reverts commit 68f903c6dd7403a4cf280cf71ee02d20345938b5.
 2020-02-27 10:17:29 -08:00
Eddie Hung
f858219c4e Cleanup tests 2020-02-27 10:17:29 -08:00
Eddie Hung
717fb492b3 Update bug1630.ys to use -lut 4 instead of lut file 2020-02-27 10:17:29 -08:00
Eddie Hung
bc97e64b21 Fix tests/arch/xilinx/fsm.ys to count flops only 2020-02-27 10:17:29 -08:00
Eddie Hung
977262c803 Update simple_abc9 tests 2020-02-27 10:17:29 -08:00
Alberto Gonzalez
f80fe8dc22
Change attribute search value to specify precise location instead of simple line number. 2020-02-24 02:41:08 +00:00
Alberto Gonzalez
2c2f092c90
Change attribute search value to specify precise location instead of simple line number. 2020-02-24 01:39:36 +00:00
Eddie Hung
760096e8d2
Merge pull request #1703 from YosysHQ/eddie/specify_improve 
Improve specify parser
 2020-02-21 09:15:17 -08:00
Claire Wolf
cd044a2bb6
Merge pull request #1642 from jjj11x/jjj11x/sv-enum 
Enum support
 2020-02-20 18:17:25 +01:00
Eddie Hung
1d401a7991 clean: ignore specify-s inside cells when determining whether to keep 2020-02-19 10:45:10 -08:00
Jeff Wang
d12ba42a74 add attributes for enumerated values in ilang 
- information also useful for strongly-typed enums (not implemented)
- resolves enum values in ilang part of #1594
- still need to output enums to VCD (or better yet FST) files
 2020-02-17 04:42:42 -05:00
Marcin Kościelnicki
cd60f079d6 tests/aiger: Add missing .gitignore 2020-02-15 19:52:21 +01:00
Miodrag Milanović
c7af1b22ba
Merge pull request #1701 from nakengelhardt/rpc-test 
make rpc frontend unix socket test less fragile
 2020-02-14 12:06:37 +01:00
Eddie Hung
d20c1dac73 verilog: ignore ranges too without -specify 2020-02-13 17:58:43 -08:00
Eddie Hung
3065d4092e Fine tune #1699 tests 2020-02-13 15:14:58 -08:00
Eddie Hung
6b58c1820c verilog: improve specify support when not in -specify mode 2020-02-13 13:27:15 -08:00
Eddie Hung
2e51dc1856 verilog: ignore '&&&' when not in -specify mode 2020-02-13 13:06:13 -08:00
Eddie Hung
b523ecf2f4 specify: system timing checks to accept min:typ:max triple 2020-02-13 12:42:15 -08:00
Eddie Hung
7cfdf4ffa7 verilog: fix $specify3 check 2020-02-13 12:42:04 -08:00
Eddie Hung
ebb11bcea4 iopadmap: move \init attributes from outpad output to its input 2020-02-13 12:05:14 -08:00
N. Engelhardt
c2467fdd55 make rpc frontend unix socket test less fragile 2020-02-13 20:52:22 +01:00
N. Engelhardt
e069259a53
Merge pull request #1679 from thasti/delay-parsing 
Fix crash on wire declaration with delay
 2020-02-13 12:01:27 +01:00
Eddie Hung
d4ff5b2d00
Merge pull request #1670 from rodrigomelo9/master 
$readmem[hb] file inclusion is now relative to the Verilog file
 2020-02-10 08:31:01 -08:00
Marcin Kościelnicki
89adef352f xilinx: Add support for LUT RAM on LUT4-based devices. 
There are multiple other kinds of RAMs supported on these devices, but
RAM16X1D is the only dual-port one.

Fixes #1549
 2020-02-07 09:03:22 +01:00
Marcin Kościelnicki
d48950d92d xilinx: Initial support for LUT4 devices. 
Adds support for mapping logic, including LUTs, wide LUTs, and carry
chains.

Fixes #1547
 2020-02-07 09:03:22 +01:00