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verilog: ignore '&&&' when not in -specify mode

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This commit is contained in:
Eddie Hung 2020-02-13 13:06:13 -08:00
parent b523ecf2f4
commit 2e51dc1856
3 changed files with 12 additions and 5 deletions
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6
tests/various/specify.v
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@ -51,3 +51,9 @@ specify
$setuphold(d, posedge clk, 1:2:3, 4:5:6);
endspecify
endmodule
module test5(input clk, d, e, output q);
specify
$setup(d, posedge clk &&& e, 1:2:3);
endspecify
endmodule