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opt_expr: add $alu tests

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Eddie Hung 2020-03-19 14:57:10 -07:00
parent 8d1fa0e3b9
commit 5e2562f1a2
1 changed files with 63 additions and 0 deletions
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tests/opt/opt_expr_alu.ys Normal file
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read_verilog <<EOT
module test(input a, output [1:0] y);
assign y = {a,1'b0} + 1'b1;
endmodule
EOT
alumacc
equiv_opt opt_expr -fine
design -load postopt
select -assert-count 1 t:$pos
select -assert-count none t:$pos t:* %D
design -reset
read_verilog <<EOT
module test(input a, output [1:0] y);
assign y = {a,1'b1} + 1'b1;
endmodule
EOT
alumacc
select -assert-count 1 t:$alu
select -assert-count none t:$alu t:* %D
design -reset
read_verilog <<EOT
module test(input a, output [1:0] y);
assign y = {a,1'b1} - 1'b1;
endmodule
EOT
equiv_opt opt_expr -fine
design -load postopt
select -assert-count 1 t:$pos
select -assert-count none t:$pos t:* %D
design -reset
read_verilog <<EOT
module test(input a, output [3:0] y);
assign y = {a,3'b101} - 1'b1;
endmodule
EOT
equiv_opt opt_expr -fine
design -load postopt
select -assert-count 1 t:$pos
select -assert-count none t:$pos t:* %D
design -reset
read_verilog <<EOT
module test(input a, output [3:0] y);
assign y = {a,3'b101} - 1'b1;
endmodule
EOT
alumacc
equiv_opt opt_expr -fine
design -load postopt
select -assert-count 1 t:$pos
select -assert-count none t:$pos t:* %D