mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 00:55:32 +00:00
Code Activity

Merge pull request #1642 from jjj11x/jjj11x/sv-enum

Browse source 
Enum support
This commit is contained in:
Claire Wolf 2020-02-20 18:17:25 +01:00 • committed by GitHub
commit cd044a2bb6
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
10 changed files with 410 additions and 19 deletions
Download patch file Download diff file Expand all files Collapse all files

47
tests/svtypes/enum_simple.sv Normal file
View file

@ -0,0 +1,47 @@
module enum_simple(input clk, input rst);
enum {s0, s1, s2, s3} test_enum;
typedef enum logic [1:0] {
ts0, ts1, ts2, ts3
} states_t;
(states_t) state;
(states_t) enum_const = ts1;
always @(posedge clk) begin
if (rst) begin
test_enum <= s3;
state <= ts0;
end else begin
//test_enum
if (test_enum == s0)
test_enum <= s1;
else if (test_enum == s1)
test_enum <= s2;
else if (test_enum == s2)
test_enum <= s3;
else if (test_enum == s3)
test_enum <= s0;
else
assert(1'b0); //should be unreachable
//state
if (state == ts0)
state <= ts1;
else if (state == ts1)
state <= ts2;
else if (state == ts2)
state <= ts0;
else
assert(1'b0); //should be unreachable
end
end
always @(*) begin
assert(state != 2'h3);
assert(s0 == '0);
assert(ts0 == '0);
assert(enum_const == ts1);
end
endmodule

5
tests/svtypes/enum_simple.ys Normal file
View file

@ -0,0 +1,5 @@
read_verilog -sv enum_simple.sv
hierarchy; proc; opt
sat -verify -seq 1 -set-at 1 rst 1 -tempinduct -prove-asserts -show-all

3
tests/svtypes/typedef_package.sv
View file

@ -1,11 +1,14 @@
package pkg;
typedef logic [7:0] uint8_t;
typedef enum logic [7:0] {bb=8'hBB} enum8_t;
endpackage
module top;
(* keep *) (pkg::uint8_t) a = 8'hAA;
(* keep *) (pkg::enum8_t) b_enum = pkg::bb;
always @* assert(a == 8'hAA);
always @* assert(b_enum == 8'hBB);
endmodule

14
tests/svtypes/typedef_scopes.sv
View file

@ -1,23 +1,35 @@
typedef logic [3:0] outer_uint4_t;
typedef enum logic {s0, s1} outer_enum_t;
module top;
(outer_uint4_t) u4_i = 8'hA5;
(outer_enum_t) enum4_i = s0;
always @(*) assert(u4_i == 4'h5);
always @(*) assert(enum4_i == 1'b0);
typedef logic [3:0] inner_type;
typedef enum logic [2:0] {s2=2, s3, s4} inner_enum_t;
(inner_type) inner_i1 = 8'h5A;
(inner_enum_t) inner_enum1 = s3;
always @(*) assert(inner_i1 == 4'hA);
always @(*) assert(inner_enum1 == 3'h3);
if (1) begin: genblock
typedef logic [7:0] inner_type;
(inner_type) inner_gb_i = 8'hA5;
parameter (inner_type) inner_const = 8'hA5;
typedef enum logic [2:0] {s5=5, s6, s7} inner_enum_t;
(inner_type) inner_gb_i = inner_const; //8'hA5;
(inner_enum_t) inner_gb_enum1 = s7;
always @(*) assert(inner_gb_i == 8'hA5);
always @(*) assert(inner_gb_enum1 == 3'h7);
end
(inner_type) inner_i2 = 8'h42;
(inner_enum_t) inner_enum2 = s4;
always @(*) assert(inner_i2 == 4'h2);
always @(*) assert(inner_enum2 == 3'h4);
endmodule