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Merge pull request #1703 from YosysHQ/eddie/specify_improve

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Improve specify parser
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Eddie Hung 2020-02-21 09:15:17 -08:00 • committed by GitHub
commit 760096e8d2
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8 changed files with 170 additions and 52 deletions
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29
tests/various/specify.v
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@ -7,11 +7,9 @@ module test (
if (EN) Q <= D;
specify
`ifndef SKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS
if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4);
$setup(D, posedge CLK &&& EN, 5);
$hold(posedge CLK, D &&& EN, 6);
`endif
endspecify
endmodule
@ -37,3 +35,30 @@ specify
(posedge clk *> (q +: d)) = (3,1);
endspecify
endmodule
module test3(input clk, input [1:0] d, output [1:0] q);
specify
(posedge clk => (q +: d)) = (3,1);
(posedge clk *> (q +: d)) = (3,1);
endspecify
endmodule
module test4(input clk, d, output q);
specify
$setup(d, posedge clk, 1:2:3);
$setuphold(d, posedge clk, 1:2:3, 4:5:6);
endspecify
endmodule
module test5(input clk, d, e, output q);
specify
$setup(d, posedge clk &&& e, 1:2:3);
endspecify
endmodule
module test6(input clk, d, e, output q);
specify
(d[0] *> q[0]) = (3,1);
(posedge clk[0] => (q[0] +: d[0])) = (3,1);
endspecify
endmodule

21
tests/various/specify.ys
View file

@ -55,4 +55,23 @@ equiv_induct -seq 5
equiv_status -assert
design -reset
read_verilog -DSKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS specify.v
read_verilog -specify <<EOT
(* blackbox *)
module test7_sub(input i, output o);
specify
(i => o) = 1;
endspecify
assign o = ~i;
endmodule
module test7(input i, output o);
wire w;
test7_sub unused(i, w);
test7_sub used(i, o);
endmodule
EOT
hierarchy
cd test7
clean
select -assert-count 1 c:used
select -assert-none c:* c:used %d