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verilog: ignore ranges too without -specify

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This commit is contained in:
Eddie Hung 2020-02-13 17:58:43 -08:00
parent 6b58c1820c
commit d20c1dac73
2 changed files with 9 additions and 1 deletions
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7
tests/various/specify.v
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@ -55,3 +55,10 @@ specify
$setup(d, posedge clk &&& e, 1:2:3);
endspecify
endmodule
module test6(input clk, d, e, output q);
specify
(d[0] *> q[0]) = (3,1);
(posedge clk[0] => (q[0] +: d[0])) = (3,1);
endspecify
endmodule