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ast: fixes #1710; do not generate RTLIL for unreachable ternary

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Eddie Hung 2020-02-27 16:55:55 -08:00
parent 825b96fdcf
commit 5bba9c3640
2 changed files with 52 additions and 9 deletions
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30
tests/various/bug1710.ys Normal file
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@ -0,0 +1,30 @@
logger -werror "out of bounds"
read_verilog <<EOT
module Example;
parameter FLAG = 1;
wire [3:0] inp;
reg out1;
initial out1 = FLAG ? &inp[2:0] : &inp[4:0];
reg out2;
initial
if (FLAG)
out2 = &inp[2:0];
else
out2 = &inp[4:0];
wire out3;
assign out3 = FLAG ? &inp[2:0] : &inp[4:0];
wire out4;
generate
if (FLAG)
assign out4 = &inp[2:0];
else
assign out4 = &inp[4:0];
endgenerate
endmodule
EOT