Fix partsel expr bit width handling and add test case

Signed-off-by: Claire Wolf <claire@symbioticeda.com>

tests/simple/partsel.v

@@ -60,3 +60,7 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+module partsel_test003(input [2:0] a, b, input [31:0] din, output [3:0] dout);
+assign dout = din[a*b +: 2];
+endmodule