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verilog: improve specify support when not in -specify mode

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This commit is contained in:
Eddie Hung 2020-02-13 13:27:15 -08:00
parent 2e51dc1856
commit 6b58c1820c
3 changed files with 8 additions and 16 deletions
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2
tests/various/specify.v
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@ -7,11 +7,9 @@ module test (
if (EN) Q <= D;
specify
`ifndef SKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS
if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4);
$setup(D, posedge CLK &&& EN, 5);
$hold(posedge CLK, D &&& EN, 6);
`endif
endspecify
endmodule

2
tests/various/specify.ys
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@ -55,4 +55,4 @@ equiv_induct -seq 5
equiv_status -assert
design -reset
read_verilog -DSKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS specify.v
read_verilog specify.v