Merge pull request #1724 from YosysHQ/eddie/abc9_specify

abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries

tests/arch/ecp5/bug1630.ys

@@ -1,2 +1,2 @@
 read_ilang bug1630.il.gz
-abc9 -lut +/ecp5/abc9_5g.lut
+abc9 -lut 4

tests/simple_abc9/abc.box

@@ -1,2 +0,0 @@
-MUXF8 1 0 3 1
-1 1 1

tests/simple_abc9/abc9.v

@@ -213,8 +213,13 @@ module arbiter (clk, rst, request, acknowledge, grant, grant_valid, grant_encode
   input rst;
 endmodule
 
-(* abc9_box_id=1, whitebox *)
+(* abc9_box, blackbox *)
 module MUXF8(input I0, I1, S, output O);
+specify
+    (I0 => O) = 0;
+    (I1 => O) = 0;
+    (S => O) = 0;
+endspecify
 endmodule
 
 // Citation: https://github.com/alexforencich/verilog-ethernet

tests/simple_abc9/run-test.sh

@@ -25,8 +25,8 @@ exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v *.sv EXTRA_FLAGS="-n 300 -p
     synth -run coarse; \
     opt -full; \
     techmap; \
-    abc9 -lut 4 -box ../abc.box; \
+    abc9 -lut 4; \
     clean; \
     check -assert; \
     select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%; \
-    setattr -mod -unset whitebox'"
+    setattr -mod -unset blackbox'"

tests/various/pmux2shiftx.v

@@ -33,7 +33,7 @@ module pmux2shiftx_test (
 	end
 endmodule
 
-module issue01135(input [7:0] i, output o);
+module issue01135(input [7:0] i, output reg o);
 always @*
 case (i[6:3])
     4: o <= i[0];