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deminout: Don't demote inouts with unused bits

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Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2020-02-25 14:14:45 +00:00
parent 6edca05793
commit 5cae9c6e16
2 changed files with 15 additions and 2 deletions
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14
tests/various/deminout_unused.ys Normal file
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read_verilog <<EOT
module top(input clk, inout [7:0] x);
reg [3:0] ctr;
always @(posedge clk) ctr <= ctr + 1'b1;
assign x[7:4] = ctr;
endmodule
EOT
proc
tribuf
deminout
select -assert-count 1 i:x o:x %i