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Code Activity
7918 commits 122 branches 59 tags 72 MiB
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842 commits

Author SHA1 Message Date
Eddie Hung
d86d073ad6 Add testcase 2019-12-13 10:26:30 -08:00
Eddie Hung
7e5602ad17
Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr 
Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
 2019-12-09 17:38:48 -08:00
Eddie Hung
eff858cd33 unmap $__ICE40_CARRY_WRAPPER in test 2019-12-09 14:20:35 -08:00
Eddie Hung
e05372778a ice40_wrapcarry to really preserve attributes via -unwrap option 2019-12-09 11:48:28 -08:00
Eddie Hung
946d5854c0 Drop keep=0 attributes on SB_CARRY 2019-12-06 17:27:47 -08:00
Jan Kowalewski
dcb30b5f4a tests: arch: xilinx: Change order of arguments in macc.sh 2019-12-06 09:15:49 +01:00
Eddie Hung
d8fbf88980 Add WIP test for unwrapping $__ICE40_CARRY_WRAPPER 2019-12-05 07:01:02 -08:00
Marcin Kościelnicki
2abe38e73e
iopadmap: Refactor and fix tristate buffer mapping. (#1527) 
The previous code for rerouting wires when inserting tristate buffers
was overcomplicated and didn't handle all cases correctly (in
particular, only cell connections were rewired — internal connections
were not).
 2019-12-04 08:44:08 +01:00
Eddie Hung
67f1ce2d43 Check SB_CARRY name also preserved 2019-12-03 14:51:39 -08:00
Eddie Hung
8de17877d4 Add testcase 2019-12-03 14:48:00 -08:00
Clifford Wolf
2ec6d832dc
Merge pull request #1524 from pepijndevos/gowindffinit 
Gowin: add and test DFF init values
 2019-12-03 08:43:18 -08:00
Pepijn de Vos
a7d34a7cb5 update test 2019-12-03 16:56:15 +01:00
Pepijn de Vos
a3b25b4af8 Use -match-init to not synth contradicting init values 2019-12-03 15:12:25 +01:00
David Shah
e9ce4e658b abc9: Fix breaking of SCCs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-01 20:44:56 +00:00
Eddie Hung
6464dc35ec
Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd 
xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder
 2019-11-27 08:00:22 -08:00
Clifford Wolf
f43c0bd8ba
Merge pull request #1534 from YosysHQ/mwk/opt_share-fix 
opt_share: Fix handling of fine cells.
 2019-11-27 11:23:16 +01:00
Eddie Hung
de3476cc23 No need for -abc9 2019-11-26 23:08:14 -08:00
Marcin Kościelnicki
fdcbda195b opt_share: Fix handling of fine cells. 
Fixes #1525.
 2019-11-27 08:01:07 +01:00
Eddie Hung
4a0198128e Add citation 2019-11-26 22:51:16 -08:00
Eddie Hung
15042eaf57 Remove notes 2019-11-26 22:41:35 -08:00
Eddie Hung
222e199b73 Add testcase derived from fastfir_dynamictaps benchmark 2019-11-26 21:26:30 -08:00
Marcin Kościelnicki
6cdea425b8 clkbufmap: Add support for inverters in clock path. 2019-11-25 20:40:39 +01:00
Marcin Kościelnicki
7562e7304e xilinx: Use INV instead of LUT1 when applicable 2019-11-25 20:40:39 +01:00
Pepijn de Vos
72d03dc910 attempt to fix formatting 2019-11-25 14:50:34 +01:00
Pepijn de Vos
6c79abbf5a gowin: add and test dff init values 2019-11-25 14:33:21 +01:00
Clifford Wolf
72d2ef6fd0
Merge pull request #1511 from YosysHQ/dave/always 
sv: Error checking for always_comb, always_latch and always_ff
 2019-11-22 15:32:29 +01:00
Marcin Kościelnicki
e110df9c48 gowin: Remove show command from tests. 2019-11-22 14:49:35 +01:00
David Shah
49b670ca38 sv: Add tests for SV always types 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-21 21:06:28 +00:00
Clifford Wolf
7ea0a5937b
Merge pull request #1449 from pepijndevos/gowin 
Improvements for gowin support
 2019-11-19 17:29:27 +01:00
Marcin Kościelnicki
15232a48af Fix #1462, #1480. 2019-11-19 08:57:39 +01:00
Marcin Kościelnicki
38e72d6e13 Fix #1496. 2019-11-18 04:16:48 +01:00
Pepijn de Vos
32f0296df1 Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin 2019-11-16 12:43:17 +01:00
Pepijn de Vos
ab8c521030 fix fsm test with proper clock enable polarity 2019-11-11 17:51:26 +01:00
Miodrag Milanovic
3e0ffe05a7 Fixed tests 2019-11-11 15:41:33 +01:00
Pepijn de Vos
0e5dbc4abc fix wide luts 2019-11-06 19:48:18 +01:00
Pepijn de Vos
df8390f5df don't cound exact luts in big muxes; futile and fragile 2019-10-30 14:58:25 +01:00
Pepijn de Vos
903f997391 add tristate buffer and test 2019-10-28 15:18:01 +01:00
Pepijn de Vos
9517525224 do not use wide luts in testcase 2019-10-28 14:40:12 +01:00
Pepijn de Vos
8226f2db0b ALU sim tweaks 2019-10-24 13:39:43 +02:00
Pepijn de Vos
83fbfe0964 Add some tests 
Copied from Efinix.

* fsm is broken
* latch and tribuf are not implemented yet
* memory maps to dram
 2019-10-21 16:25:15 +02:00
Miodrag Milanovic
190b40341a fixed error 2019-10-18 13:15:36 +02:00
Miodrag Milanovic
9bd9db56c8 Unify verilog style 2019-10-18 12:50:24 +02:00
Miodrag Milanovic
12383f37b2 Common memory test now shared 2019-10-18 12:33:35 +02:00
Miodrag Milanovic
477702b8c9 Remove not needed tests 2019-10-18 12:20:35 +02:00
Miodrag Milanovic
5603595e5c Share common tests 2019-10-18 12:19:59 +02:00
Miodrag Milanovic
ab98f2dccf fix yosys path 2019-10-18 11:18:53 +02:00
Miodrag Milanovic
56f9482675 Fix path to yosys 2019-10-18 11:12:03 +02:00
Miodrag Milanovic
c2ec7ca703 Moved all tests in arch sub directory 2019-10-18 11:06:12 +02:00
Miodrag Milanovic
3c41599ee1 Add async2sync 2019-10-18 11:00:27 +02:00
Miodrag Milanović
b4d7650548
Merge branch 'master' into mmicko/efinix 2019-10-18 10:54:28 +02:00