mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
Share common tests
This commit is contained in:
Miodrag Milanovic
parent
ab98f2dccf
commit
5603595e5c
103 changed files with 179 additions and 1317 deletions
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@ -1,4 +1,4 @@
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read_verilog add_sub.v
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read_verilog ../common/add_sub.v
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hierarchy -top top
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proc
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equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
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@ -1,4 +1,4 @@
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read_verilog counter.v
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read_verilog ../common/counter.v
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hierarchy -top top
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proc
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flatten
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@ -1,4 +1,4 @@
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read_verilog dffs.v
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read_verilog ../common/dffs.v
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design -save read
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hierarchy -top dff
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@ -1,4 +1,4 @@
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read_verilog fsm.v
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read_verilog ../common/fsm.v
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hierarchy -top fsm
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proc
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#flatten
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@ -1,4 +1,4 @@
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read_verilog latches.v
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read_verilog ../common/latches.v
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design -save read
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hierarchy -top latchp
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11
tests/arch/anlogic/logic.ys
Normal file
11
tests/arch/anlogic/logic.ys
Normal file
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@ -0,0 +1,11 @@
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read_verilog ../common/logic.v
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hierarchy -top top
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proc
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equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:AL_MAP_LUT1
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select -assert-count 6 t:AL_MAP_LUT2
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select -assert-count 2 t:AL_MAP_LUT4
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select -assert-none t:AL_MAP_LUT1 t:AL_MAP_LUT2 t:AL_MAP_LUT4 %% t:* %D
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@ -1,4 +1,4 @@
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read_verilog mux.v
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read_verilog ../common/mux.v
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design -save read
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hierarchy -top mux2
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@ -1,4 +1,4 @@
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read_verilog shifter.v
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read_verilog ../common/shifter.v
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hierarchy -top top
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proc
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flatten
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@ -1,8 +0,0 @@
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module tristate (en, i, o);
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input en;
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input i;
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output o;
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assign o = en ? i : 1'bz;
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endmodule
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@ -1,4 +1,4 @@
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read_verilog tribuf.v
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read_verilog ../common/tribuf.v
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hierarchy -top tristate
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proc
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flatten
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@ -1,13 +0,0 @@
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module top
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(
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input [3:0] x,
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input [3:0] y,
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output [3:0] A,
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output [3:0] B
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);
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assign A = x + y;
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assign B = x - y;
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endmodule
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@ -1,4 +1,4 @@
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read_verilog add_sub.v
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read_verilog ../common/add_sub.v
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hierarchy -top top
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proc
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equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
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@ -1,4 +1,4 @@
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read_verilog adffs.v
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read_verilog ../common/adffs.v
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design -save read
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hierarchy -top adff
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@ -1,17 +0,0 @@
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module top (
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out,
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clk,
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reset
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);
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output [7:0] out;
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input clk, reset;
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reg [7:0] out;
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always @(posedge clk, posedge reset)
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if (reset) begin
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out <= 8'b0 ;
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end else
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out <= out + 1;
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endmodule
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@ -1,4 +1,4 @@
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read_verilog counter.v
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read_verilog ../common/counter.v
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hierarchy -top top
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proc
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flatten
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@ -1,15 +0,0 @@
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module dff
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( input d, clk, output reg q );
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always @( posedge clk )
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q <= d;
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endmodule
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module dffe
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( input d, clk, en, output reg q );
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initial begin
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q = 0;
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end
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always @( posedge clk )
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if ( en )
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q <= d;
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endmodule
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@ -1,4 +1,4 @@
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read_verilog dffs.v
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read_verilog ../common/dffs.v
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design -save read
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hierarchy -top dff
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@ -1,55 +0,0 @@
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module fsm (
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clock,
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reset,
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req_0,
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req_1,
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gnt_0,
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gnt_1
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);
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input clock,reset,req_0,req_1;
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output gnt_0,gnt_1;
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wire clock,reset,req_0,req_1;
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reg gnt_0,gnt_1;
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parameter SIZE = 3 ;
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parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
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reg [SIZE-1:0] state;
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reg [SIZE-1:0] next_state;
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always @ (posedge clock)
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begin : FSM
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if (reset == 1'b1) begin
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state <= #1 IDLE;
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gnt_0 <= 0;
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gnt_1 <= 0;
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end else
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case(state)
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IDLE : if (req_0 == 1'b1) begin
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state <= #1 GNT0;
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gnt_0 <= 1;
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end else if (req_1 == 1'b1) begin
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gnt_1 <= 1;
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state <= #1 GNT0;
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end else begin
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state <= #1 IDLE;
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end
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GNT0 : if (req_0 == 1'b1) begin
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state <= #1 GNT0;
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end else begin
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gnt_0 <= 0;
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state <= #1 IDLE;
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end
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GNT1 : if (req_1 == 1'b1) begin
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state <= #1 GNT2;
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gnt_1 <= req_0;
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end
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GNT2 : if (req_0 == 1'b1) begin
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state <= #1 GNT1;
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gnt_1 <= req_1;
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end
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default : state <= #1 IDLE;
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endcase
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end
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endmodule
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@ -1,4 +1,4 @@
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read_verilog fsm.v
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read_verilog ../common/fsm.v
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hierarchy -top fsm
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proc
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flatten
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@ -1,24 +0,0 @@
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module latchp
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( input d, clk, en, output reg q );
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always @*
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if ( en )
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q <= d;
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endmodule
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module latchn
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( input d, clk, en, output reg q );
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always @*
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if ( !en )
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q <= d;
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endmodule
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module latchsr
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( input d, clk, en, clr, pre, output reg q );
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always @*
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if ( clr )
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q <= 1'b0;
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else if ( pre )
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q <= 1'b1;
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else if ( en )
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q <= d;
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endmodule
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@ -1,5 +1,4 @@
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read_verilog latches.v
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read_verilog ../common/latches.v
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design -save read
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hierarchy -top latchp
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@ -1,4 +1,4 @@
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read_verilog logic.v
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read_verilog ../common/logic.v
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hierarchy -top top
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proc
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equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
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@ -1,4 +1,4 @@
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read_verilog mul.v
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read_verilog ../common/mul.v
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hierarchy -top top
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proc
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# Blocked by issue #1358 (Missing ECP5 simulation models)
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@ -1,66 +0,0 @@
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module mux2 (S,A,B,Y);
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input S;
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input A,B;
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output reg Y;
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always @(*)
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Y = (S)? B : A;
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endmodule
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module mux4 ( S, D, Y );
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input[1:0] S;
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input[3:0] D;
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output Y;
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reg Y;
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wire[1:0] S;
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wire[3:0] D;
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always @*
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begin
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case( S )
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0 : Y = D[0];
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1 : Y = D[1];
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2 : Y = D[2];
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3 : Y = D[3];
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endcase
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end
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endmodule
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module mux8 ( S, D, Y );
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input[2:0] S;
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input[7:0] D;
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output Y;
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reg Y;
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wire[2:0] S;
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wire[7:0] D;
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always @*
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begin
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case( S )
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0 : Y = D[0];
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1 : Y = D[1];
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2 : Y = D[2];
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3 : Y = D[3];
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4 : Y = D[4];
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5 : Y = D[5];
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6 : Y = D[6];
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7 : Y = D[7];
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endcase
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end
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endmodule
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module mux16 (D, S, Y);
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input [15:0] D;
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input [3:0] S;
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output Y;
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assign Y = D[S];
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endmodule
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@ -1,4 +1,4 @@
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read_verilog mux.v
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read_verilog ../common/mux.v
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design -save read
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hierarchy -top mux2
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@ -1,16 +0,0 @@
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module top (
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out,
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clk,
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in
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);
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output [7:0] out;
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input signed clk, in;
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reg signed [7:0] out = 0;
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always @(posedge clk)
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begin
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out <= out >> 1;
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out[7] <= in;
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end
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endmodule
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@ -1,4 +1,4 @@
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read_verilog shifter.v
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read_verilog ../common/shifter.v
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hierarchy -top top
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proc
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flatten
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@ -1,8 +0,0 @@
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module tristate (en, i, o);
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input en;
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input i;
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output o;
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assign o = en ? i : 1'bz;
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endmodule
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@ -1,4 +1,4 @@
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read_verilog tribuf.v
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read_verilog ../common/tribuf.v
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hierarchy -top tristate
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proc
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flatten
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@ -1,13 +0,0 @@
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module top
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(
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input [3:0] x,
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input [3:0] y,
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output [3:0] A,
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output [3:0] B
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);
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assign A = x + y;
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assign B = x - y;
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endmodule
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@ -1,4 +1,4 @@
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read_verilog add_sub.v
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read_verilog ../common/add_sub.v
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hierarchy -top top
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proc
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equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
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@ -1,47 +0,0 @@
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module adff
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( input d, clk, clr, output reg q );
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initial begin
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q = 0;
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end
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always @( posedge clk, posedge clr )
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if ( clr )
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q <= 1'b0;
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else
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q <= d;
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endmodule
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module adffn
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( input d, clk, clr, output reg q );
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initial begin
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q = 0;
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end
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always @( posedge clk, negedge clr )
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if ( !clr )
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q <= 1'b0;
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else
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q <= d;
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endmodule
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module dffs
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( input d, clk, pre, clr, output reg q );
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initial begin
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q = 0;
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end
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always @( posedge clk )
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if ( pre )
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q <= 1'b1;
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else
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q <= d;
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endmodule
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module ndffnr
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( input d, clk, pre, clr, output reg q );
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initial begin
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q = 0;
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end
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always @( negedge clk )
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if ( !clr )
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q <= 1'b0;
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else
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q <= d;
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endmodule
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@ -1,4 +1,4 @@
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read_verilog adffs.v
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read_verilog ../common/adffs.v
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design -save read
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hierarchy -top adff
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|
|
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|
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@ -1,17 +0,0 @@
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module top (
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out,
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clk,
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reset
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);
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output [7:0] out;
|
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input clk, reset;
|
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reg [7:0] out;
|
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|
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always @(posedge clk, posedge reset)
|
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if (reset) begin
|
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out <= 8'b0 ;
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end else
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out <= out + 1;
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|
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|
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endmodule
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|
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@ -1,4 +1,4 @@
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read_verilog counter.v
|
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read_verilog ../common/counter.v
|
||||
hierarchy -top top
|
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proc
|
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flatten
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|
|
|
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|
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@ -1,15 +0,0 @@
|
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module dff
|
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( input d, clk, output reg q );
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always @( posedge clk )
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q <= d;
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endmodule
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|
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module dffe
|
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( input d, clk, en, output reg q );
|
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initial begin
|
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q = 0;
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end
|
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always @( posedge clk )
|
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if ( en )
|
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q <= d;
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endmodule
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|
|
@ -1,4 +1,4 @@
|
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read_verilog dffs.v
|
||||
read_verilog ../common/dffs.v
|
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design -save read
|
||||
|
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hierarchy -top dff
|
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|
|
|
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|
|
@ -1,55 +0,0 @@
|
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module fsm (
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clock,
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reset,
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req_0,
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req_1,
|
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gnt_0,
|
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gnt_1
|
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);
|
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input clock,reset,req_0,req_1;
|
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output gnt_0,gnt_1;
|
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wire clock,reset,req_0,req_1;
|
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reg gnt_0,gnt_1;
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|
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parameter SIZE = 3 ;
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parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
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|
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reg [SIZE-1:0] state;
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reg [SIZE-1:0] next_state;
|
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|
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always @ (posedge clock)
|
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begin : FSM
|
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if (reset == 1'b1) begin
|
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state <= #1 IDLE;
|
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gnt_0 <= 0;
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gnt_1 <= 0;
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||||
end else
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||||
case(state)
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IDLE : if (req_0 == 1'b1) begin
|
||||
state <= #1 GNT0;
|
||||
gnt_0 <= 1;
|
||||
end else if (req_1 == 1'b1) begin
|
||||
gnt_1 <= 1;
|
||||
state <= #1 GNT0;
|
||||
end else begin
|
||||
state <= #1 IDLE;
|
||||
end
|
||||
GNT0 : if (req_0 == 1'b1) begin
|
||||
state <= #1 GNT0;
|
||||
end else begin
|
||||
gnt_0 <= 0;
|
||||
state <= #1 IDLE;
|
||||
end
|
||||
GNT1 : if (req_1 == 1'b1) begin
|
||||
state <= #1 GNT2;
|
||||
gnt_1 <= req_0;
|
||||
end
|
||||
GNT2 : if (req_0 == 1'b1) begin
|
||||
state <= #1 GNT1;
|
||||
gnt_1 <= req_1;
|
||||
end
|
||||
default : state <= #1 IDLE;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
read_verilog fsm.v
|
||||
read_verilog ../common/fsm.v
|
||||
hierarchy -top fsm
|
||||
proc
|
||||
flatten
|
||||
|
|
|
|||
|
|
@ -1,24 +0,0 @@
|
|||
module latchp
|
||||
( input d, clk, en, output reg q );
|
||||
always @*
|
||||
if ( en )
|
||||
q <= d;
|
||||
endmodule
|
||||
|
||||
module latchn
|
||||
( input d, clk, en, output reg q );
|
||||
always @*
|
||||
if ( !en )
|
||||
q <= d;
|
||||
endmodule
|
||||
|
||||
module latchsr
|
||||
( input d, clk, en, clr, pre, output reg q );
|
||||
always @*
|
||||
if ( clr )
|
||||
q <= 1'b0;
|
||||
else if ( pre )
|
||||
q <= 1'b1;
|
||||
else if ( en )
|
||||
q <= d;
|
||||
endmodule
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
read_verilog latches.v
|
||||
read_verilog ../common/latches.v
|
||||
design -save read
|
||||
|
||||
hierarchy -top latchp
|
||||
|
|
|
|||
|
|
@ -1,18 +0,0 @@
|
|||
module top
|
||||
(
|
||||
input [0:7] in,
|
||||
output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
|
||||
);
|
||||
|
||||
assign B1 = in[0] & in[1];
|
||||
assign B2 = in[0] | in[1];
|
||||
assign B3 = in[0] ~& in[1];
|
||||
assign B4 = in[0] ~| in[1];
|
||||
assign B5 = in[0] ^ in[1];
|
||||
assign B6 = in[0] ~^ in[1];
|
||||
assign B7 = ~in[0];
|
||||
assign B8 = in[0];
|
||||
assign B9 = in[0:1] && in [2:3];
|
||||
assign B10 = in[0:1] || in [2:3];
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
read_verilog logic.v
|
||||
read_verilog ../common/logic.v
|
||||
hierarchy -top top
|
||||
proc
|
||||
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
|
||||
|
|
|
|||
|
|
@ -1,65 +0,0 @@
|
|||
module mux2 (S,A,B,Y);
|
||||
input S;
|
||||
input A,B;
|
||||
output reg Y;
|
||||
|
||||
always @(*)
|
||||
Y = (S)? B : A;
|
||||
endmodule
|
||||
|
||||
module mux4 ( S, D, Y );
|
||||
|
||||
input[1:0] S;
|
||||
input[3:0] D;
|
||||
output Y;
|
||||
|
||||
reg Y;
|
||||
wire[1:0] S;
|
||||
wire[3:0] D;
|
||||
|
||||
always @*
|
||||
begin
|
||||
case( S )
|
||||
0 : Y = D[0];
|
||||
1 : Y = D[1];
|
||||
2 : Y = D[2];
|
||||
3 : Y = D[3];
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module mux8 ( S, D, Y );
|
||||
|
||||
input[2:0] S;
|
||||
input[7:0] D;
|
||||
output Y;
|
||||
|
||||
reg Y;
|
||||
wire[2:0] S;
|
||||
wire[7:0] D;
|
||||
|
||||
always @*
|
||||
begin
|
||||
case( S )
|
||||
0 : Y = D[0];
|
||||
1 : Y = D[1];
|
||||
2 : Y = D[2];
|
||||
3 : Y = D[3];
|
||||
4 : Y = D[4];
|
||||
5 : Y = D[5];
|
||||
6 : Y = D[6];
|
||||
7 : Y = D[7];
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module mux16 (D, S, Y);
|
||||
input [15:0] D;
|
||||
input [3:0] S;
|
||||
output Y;
|
||||
|
||||
assign Y = D[S];
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
read_verilog mux.v
|
||||
read_verilog ../common/mux.v
|
||||
design -save read
|
||||
|
||||
hierarchy -top mux2
|
||||
|
|
|
|||
|
|
@ -1,16 +0,0 @@
|
|||
module top (
|
||||
out,
|
||||
clk,
|
||||
in
|
||||
);
|
||||
output [7:0] out;
|
||||
input signed clk, in;
|
||||
reg signed [7:0] out = 0;
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
out <= out << 1;
|
||||
out[7] <= in;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
read_verilog shifter.v
|
||||
read_verilog ../common/shifter.v
|
||||
hierarchy -top top
|
||||
proc
|
||||
flatten
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
read_verilog tribuf.v
|
||||
read_verilog ../common/tribuf.v
|
||||
hierarchy -top tristate
|
||||
proc
|
||||
tribuf
|
||||
|
|
|
|||
|
|
@ -1,13 +0,0 @@
|
|||
module top
|
||||
(
|
||||
input [3:0] x,
|
||||
input [3:0] y,
|
||||
|
||||
output [3:0] A,
|
||||
output [3:0] B
|
||||
);
|
||||
|
||||
assign A = x + y;
|
||||
assign B = x - y;
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
read_verilog add_sub.v
|
||||
read_verilog ../common/add_sub.v
|
||||
hierarchy -top top
|
||||
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
|
|
|
|||
|
|
@ -1,87 +0,0 @@
|
|||
module adff
|
||||
( input d, clk, clr, output reg q );
|
||||
initial begin
|
||||
q = 0;
|
||||
end
|
||||
always @( posedge clk, posedge clr )
|
||||
if ( clr )
|
||||
q <= 1'b0;
|
||||
else
|
||||
q <= d;
|
||||
endmodule
|
||||
|
||||
module adffn
|
||||
( input d, clk, clr, output reg q );
|
||||
initial begin
|
||||
q = 0;
|
||||
end
|
||||
always @( posedge clk, negedge clr )
|
||||
if ( !clr )
|
||||
q <= 1'b0;
|
||||
else
|
||||
q <= d;
|
||||
endmodule
|
||||
|
||||
module dffs
|
||||
( input d, clk, pre, clr, output reg q );
|
||||
initial begin
|
||||
q = 0;
|
||||
end
|
||||
always @( posedge clk, posedge pre )
|
||||
if ( pre )
|
||||
q <= 1'b1;
|
||||
else
|
||||
q <= d;
|
||||
endmodule
|
||||
|
||||
module ndffnr
|
||||
( input d, clk, pre, clr, output reg q );
|
||||
initial begin
|
||||
q = 0;
|
||||
end
|
||||
always @( negedge clk, negedge pre )
|
||||
if ( !pre )
|
||||
q <= 1'b1;
|
||||
else
|
||||
q <= d;
|
||||
endmodule
|
||||
|
||||
module top (
|
||||
input clk,
|
||||
input clr,
|
||||
input pre,
|
||||
input a,
|
||||
output b,b1,b2,b3
|
||||
);
|
||||
|
||||
dffs u_dffs (
|
||||
.clk (clk ),
|
||||
.clr (clr),
|
||||
.pre (pre),
|
||||
.d (a ),
|
||||
.q (b )
|
||||
);
|
||||
|
||||
ndffnr u_ndffnr (
|
||||
.clk (clk ),
|
||||
.clr (clr),
|
||||
.pre (pre),
|
||||
.d (a ),
|
||||
.q (b1 )
|
||||
);
|
||||
|
||||
adff u_adff (
|
||||
.clk (clk ),
|
||||
.clr (clr),
|
||||
.d (a ),
|
||||
.q (b2 )
|
||||
);
|
||||
|
||||
adffn u_adffn (
|
||||
.clk (clk ),
|
||||
.clr (clr),
|
||||
.d (a ),
|
||||
.q (b3 )
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,11 +1,39 @@
|
|||
read_verilog adffs.v
|
||||
read_verilog ../common/adffs.v
|
||||
design -save read
|
||||
|
||||
hierarchy -top adff
|
||||
proc
|
||||
flatten
|
||||
equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
|
||||
equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:SB_DFFNS
|
||||
select -assert-count 2 t:SB_DFFR
|
||||
select -assert-count 1 t:SB_DFFS
|
||||
select -assert-count 2 t:SB_LUT4
|
||||
select -assert-none t:SB_DFFNS t:SB_DFFR t:SB_DFFS t:SB_LUT4 %% t:* %D
|
||||
cd adff # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:SB_DFFR
|
||||
select -assert-none t:SB_DFFR %% t:* %D
|
||||
|
||||
design -load read
|
||||
hierarchy -top adffn
|
||||
proc
|
||||
equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd adffn # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:SB_DFFR
|
||||
select -assert-count 1 t:SB_LUT4
|
||||
select -assert-none t:SB_DFFR t:SB_LUT4 %% t:* %D
|
||||
|
||||
design -load read
|
||||
hierarchy -top dffs
|
||||
proc
|
||||
equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd dffs # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:SB_DFFSS
|
||||
select -assert-none t:SB_DFFSS %% t:* %D
|
||||
|
||||
design -load read
|
||||
hierarchy -top ndffnr
|
||||
proc
|
||||
equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd ndffnr # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:SB_DFFNSR
|
||||
select -assert-count 1 t:SB_LUT4
|
||||
select -assert-none t:SB_DFFNSR t:SB_LUT4 %% t:* %D
|
||||
|
|
|
|||
|
|
@ -1,17 +0,0 @@
|
|||
module top (
|
||||
out,
|
||||
clk,
|
||||
reset
|
||||
);
|
||||
output [7:0] out;
|
||||
input clk, reset;
|
||||
reg [7:0] out;
|
||||
|
||||
always @(posedge clk, posedge reset)
|
||||
if (reset) begin
|
||||
out <= 8'b0 ;
|
||||
end else
|
||||
out <= out + 1;
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
read_verilog counter.v
|
||||
read_verilog ../common/counter.v
|
||||
hierarchy -top top
|
||||
proc
|
||||
flatten
|
||||
|
|
|
|||
|
|
@ -1,37 +0,0 @@
|
|||
module dff
|
||||
( input d, clk, output reg q );
|
||||
always @( posedge clk )
|
||||
q <= d;
|
||||
endmodule
|
||||
|
||||
module dffe
|
||||
( input d, clk, en, output reg q );
|
||||
initial begin
|
||||
q = 0;
|
||||
end
|
||||
always @( posedge clk )
|
||||
if ( en )
|
||||
q <= d;
|
||||
endmodule
|
||||
|
||||
module top (
|
||||
input clk,
|
||||
input en,
|
||||
input a,
|
||||
output b,b1,
|
||||
);
|
||||
|
||||
dff u_dff (
|
||||
.clk (clk ),
|
||||
.d (a ),
|
||||
.q (b )
|
||||
);
|
||||
|
||||
dffe u_ndffe (
|
||||
.clk (clk ),
|
||||
.en (en),
|
||||
.d (a ),
|
||||
.q (b1 )
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,10 +1,19 @@
|
|||
read_verilog dffs.v
|
||||
hierarchy -top top
|
||||
read_verilog ../common/dffs.v
|
||||
design -save read
|
||||
|
||||
hierarchy -top dff
|
||||
proc
|
||||
flatten
|
||||
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
cd dff # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:SB_DFF
|
||||
select -assert-none t:SB_DFF %% t:* %D
|
||||
|
||||
design -load read
|
||||
hierarchy -top dffe
|
||||
proc
|
||||
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd dffe # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:SB_DFFE
|
||||
select -assert-none t:SB_DFF t:SB_DFFE %% t:* %D
|
||||
select -assert-none t:SB_DFFE %% t:* %D
|
||||
|
|
@ -1,73 +0,0 @@
|
|||
module fsm (
|
||||
clock,
|
||||
reset,
|
||||
req_0,
|
||||
req_1,
|
||||
gnt_0,
|
||||
gnt_1
|
||||
);
|
||||
input clock,reset,req_0,req_1;
|
||||
output gnt_0,gnt_1;
|
||||
wire clock,reset,req_0,req_1;
|
||||
reg gnt_0,gnt_1;
|
||||
|
||||
parameter SIZE = 3 ;
|
||||
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
|
||||
|
||||
reg [SIZE-1:0] state;
|
||||
reg [SIZE-1:0] next_state;
|
||||
|
||||
always @ (posedge clock)
|
||||
begin : FSM
|
||||
if (reset == 1'b1) begin
|
||||
state <= #1 IDLE;
|
||||
gnt_0 <= 0;
|
||||
gnt_1 <= 0;
|
||||
end else
|
||||
case(state)
|
||||
IDLE : if (req_0 == 1'b1) begin
|
||||
state <= #1 GNT0;
|
||||
gnt_0 <= 1;
|
||||
end else if (req_1 == 1'b1) begin
|
||||
gnt_1 <= 1;
|
||||
state <= #1 GNT0;
|
||||
end else begin
|
||||
state <= #1 IDLE;
|
||||
end
|
||||
GNT0 : if (req_0 == 1'b1) begin
|
||||
state <= #1 GNT0;
|
||||
end else begin
|
||||
gnt_0 <= 0;
|
||||
state <= #1 IDLE;
|
||||
end
|
||||
GNT1 : if (req_1 == 1'b1) begin
|
||||
state <= #1 GNT2;
|
||||
gnt_1 <= req_0;
|
||||
end
|
||||
GNT2 : if (req_0 == 1'b1) begin
|
||||
state <= #1 GNT1;
|
||||
gnt_1 <= req_1;
|
||||
end
|
||||
default : state <= #1 IDLE;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module top (
|
||||
input clk,
|
||||
input rst,
|
||||
input a,
|
||||
input b,
|
||||
output g0,
|
||||
output g1
|
||||
);
|
||||
|
||||
fsm u_fsm ( .clock(clk),
|
||||
.reset(rst),
|
||||
.req_0(a),
|
||||
.req_1(b),
|
||||
.gnt_0(g0),
|
||||
.gnt_1(g1));
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,10 +1,10 @@
|
|||
read_verilog fsm.v
|
||||
hierarchy -top top
|
||||
read_verilog ../common/fsm.v
|
||||
hierarchy -top fsm
|
||||
proc
|
||||
flatten
|
||||
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
cd fsm # Constrain all select calls below inside the top module
|
||||
|
||||
select -assert-count 2 t:SB_DFFESR
|
||||
select -assert-count 2 t:SB_DFFSR
|
||||
|
|
|
|||
|
|
@ -1,58 +0,0 @@
|
|||
module latchp
|
||||
( input d, clk, en, output reg q );
|
||||
always @*
|
||||
if ( en )
|
||||
q <= d;
|
||||
endmodule
|
||||
|
||||
module latchn
|
||||
( input d, clk, en, output reg q );
|
||||
always @*
|
||||
if ( !en )
|
||||
q <= d;
|
||||
endmodule
|
||||
|
||||
module latchsr
|
||||
( input d, clk, en, clr, pre, output reg q );
|
||||
always @*
|
||||
if ( clr )
|
||||
q <= 1'b0;
|
||||
else if ( pre )
|
||||
q <= 1'b1;
|
||||
else if ( en )
|
||||
q <= d;
|
||||
endmodule
|
||||
|
||||
|
||||
module top (
|
||||
input clk,
|
||||
input clr,
|
||||
input pre,
|
||||
input a,
|
||||
output b,b1,b2
|
||||
);
|
||||
|
||||
|
||||
latchp u_latchp (
|
||||
.en (clk ),
|
||||
.d (a ),
|
||||
.q (b )
|
||||
);
|
||||
|
||||
|
||||
latchn u_latchn (
|
||||
.en (clk ),
|
||||
.d (a ),
|
||||
.q (b1 )
|
||||
);
|
||||
|
||||
|
||||
latchsr u_latchsr (
|
||||
.en (clk ),
|
||||
.clr (clr),
|
||||
.pre (pre),
|
||||
.d (a ),
|
||||
.q (b2 )
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,12 +1,33 @@
|
|||
read_verilog latches.v
|
||||
read_verilog ../common/latches.v
|
||||
design -save read
|
||||
|
||||
hierarchy -top latchp
|
||||
proc
|
||||
flatten
|
||||
# Can't run any sort of equivalence check because latches are blown to LUTs
|
||||
#equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
|
||||
|
||||
#design -load preopt
|
||||
synth_ice40
|
||||
cd top
|
||||
select -assert-count 4 t:SB_LUT4
|
||||
cd latchp # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:SB_LUT4
|
||||
|
||||
select -assert-none t:SB_LUT4 %% t:* %D
|
||||
|
||||
|
||||
design -load read
|
||||
hierarchy -top latchn
|
||||
proc
|
||||
# Can't run any sort of equivalence check because latches are blown to LUTs
|
||||
synth_ice40
|
||||
cd latchn # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:SB_LUT4
|
||||
|
||||
select -assert-none t:SB_LUT4 %% t:* %D
|
||||
|
||||
|
||||
design -load read
|
||||
hierarchy -top latchsr
|
||||
proc
|
||||
# Can't run any sort of equivalence check because latches are blown to LUTs
|
||||
synth_ice40
|
||||
cd latchsr # Constrain all select calls below inside the top module
|
||||
select -assert-count 2 t:SB_LUT4
|
||||
|
||||
select -assert-none t:SB_LUT4 %% t:* %D
|
||||
|
|
|
|||
|
|
@ -1,18 +0,0 @@
|
|||
module top
|
||||
(
|
||||
input [0:7] in,
|
||||
output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
|
||||
);
|
||||
|
||||
assign B1 = in[0] & in[1];
|
||||
assign B2 = in[0] | in[1];
|
||||
assign B3 = in[0] ~& in[1];
|
||||
assign B4 = in[0] ~| in[1];
|
||||
assign B5 = in[0] ^ in[1];
|
||||
assign B6 = in[0] ~^ in[1];
|
||||
assign B7 = ~in[0];
|
||||
assign B8 = in[0];
|
||||
assign B9 = in[0:1] && in [2:3];
|
||||
assign B10 = in[0:1] || in [2:3];
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
read_verilog logic.v
|
||||
read_verilog ../common/logic.v
|
||||
hierarchy -top top
|
||||
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
|
|
|
|||
|
|
@ -1,11 +0,0 @@
|
|||
module top
|
||||
(
|
||||
input [5:0] x,
|
||||
input [5:0] y,
|
||||
|
||||
output [11:0] A,
|
||||
);
|
||||
|
||||
assign A = x * y;
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
read_verilog mul.v
|
||||
read_verilog ../common/mul.v
|
||||
hierarchy -top top
|
||||
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
|
|
|
|||
|
|
@ -1,100 +0,0 @@
|
|||
module mux2 (S,A,B,Y);
|
||||
input S;
|
||||
input A,B;
|
||||
output reg Y;
|
||||
|
||||
always @(*)
|
||||
Y = (S)? B : A;
|
||||
endmodule
|
||||
|
||||
module mux4 ( S, D, Y );
|
||||
|
||||
input[1:0] S;
|
||||
input[3:0] D;
|
||||
output Y;
|
||||
|
||||
reg Y;
|
||||
wire[1:0] S;
|
||||
wire[3:0] D;
|
||||
|
||||
always @*
|
||||
begin
|
||||
case( S )
|
||||
0 : Y = D[0];
|
||||
1 : Y = D[1];
|
||||
2 : Y = D[2];
|
||||
3 : Y = D[3];
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module mux8 ( S, D, Y );
|
||||
|
||||
input[2:0] S;
|
||||
input[7:0] D;
|
||||
output Y;
|
||||
|
||||
reg Y;
|
||||
wire[2:0] S;
|
||||
wire[7:0] D;
|
||||
|
||||
always @*
|
||||
begin
|
||||
case( S )
|
||||
0 : Y = D[0];
|
||||
1 : Y = D[1];
|
||||
2 : Y = D[2];
|
||||
3 : Y = D[3];
|
||||
4 : Y = D[4];
|
||||
5 : Y = D[5];
|
||||
6 : Y = D[6];
|
||||
7 : Y = D[7];
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module mux16 (D, S, Y);
|
||||
input [15:0] D;
|
||||
input [3:0] S;
|
||||
output Y;
|
||||
|
||||
assign Y = D[S];
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module top (
|
||||
input [3:0] S,
|
||||
input [15:0] D,
|
||||
output M2,M4,M8,M16
|
||||
);
|
||||
|
||||
mux2 u_mux2 (
|
||||
.S (S[0]),
|
||||
.A (D[0]),
|
||||
.B (D[1]),
|
||||
.Y (M2)
|
||||
);
|
||||
|
||||
|
||||
mux4 u_mux4 (
|
||||
.S (S[1:0]),
|
||||
.D (D[3:0]),
|
||||
.Y (M4)
|
||||
);
|
||||
|
||||
mux8 u_mux8 (
|
||||
.S (S[2:0]),
|
||||
.D (D[7:0]),
|
||||
.Y (M8)
|
||||
);
|
||||
|
||||
mux16 u_mux16 (
|
||||
.S (S[3:0]),
|
||||
.D (D[15:0]),
|
||||
.Y (M16)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,8 +1,40 @@
|
|||
read_verilog mux.v
|
||||
read_verilog ../common/mux.v
|
||||
design -save read
|
||||
|
||||
hierarchy -top mux2
|
||||
proc
|
||||
flatten
|
||||
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
select -assert-count 19 t:SB_LUT4
|
||||
cd mux2 # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:SB_LUT4
|
||||
select -assert-none t:SB_LUT4 %% t:* %D
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux4
|
||||
proc
|
||||
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd mux4 # Constrain all select calls below inside the top module
|
||||
select -assert-count 2 t:SB_LUT4
|
||||
|
||||
select -assert-none t:SB_LUT4 %% t:* %D
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux8
|
||||
proc
|
||||
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd mux8 # Constrain all select calls below inside the top module
|
||||
select -assert-count 5 t:SB_LUT4
|
||||
|
||||
select -assert-none t:SB_LUT4 %% t:* %D
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux16
|
||||
proc
|
||||
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd mux16 # Constrain all select calls below inside the top module
|
||||
select -assert-count 11 t:SB_LUT4
|
||||
|
||||
select -assert-none t:SB_LUT4 %% t:* %D
|
||||
|
|
|
|||
|
|
@ -1,22 +0,0 @@
|
|||
module top (
|
||||
out,
|
||||
clk,
|
||||
in
|
||||
);
|
||||
output [7:0] out;
|
||||
input signed clk, in;
|
||||
reg signed [7:0] out = 0;
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
`ifndef BUG
|
||||
out <= out >> 1;
|
||||
out[7] <= in;
|
||||
`else
|
||||
|
||||
out <= out << 1;
|
||||
out[7] <= in;
|
||||
`endif
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
read_verilog shifter.v
|
||||
read_verilog ../common/shifter.v
|
||||
hierarchy -top top
|
||||
proc
|
||||
flatten
|
||||
|
|
|
|||
|
|
@ -1,23 +0,0 @@
|
|||
module tristate (en, i, o);
|
||||
input en;
|
||||
input i;
|
||||
output o;
|
||||
|
||||
assign o = en ? i : 1'bz;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module top (
|
||||
input en,
|
||||
input a,
|
||||
output b
|
||||
);
|
||||
|
||||
tristate u_tri (
|
||||
.en (en ),
|
||||
.i (a ),
|
||||
.o (b )
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,9 +1,11 @@
|
|||
read_verilog tribuf.v
|
||||
hierarchy -top top
|
||||
read_verilog ../common/tribuf.v
|
||||
hierarchy -top tristate
|
||||
proc
|
||||
tribuf
|
||||
flatten
|
||||
synth
|
||||
equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
cd tristate # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:$_TBUF_
|
||||
select -assert-none t:$_TBUF_ %% t:* %D
|
||||
|
|
|
|||
|
|
@ -1,13 +0,0 @@
|
|||
module top
|
||||
(
|
||||
input [3:0] x,
|
||||
input [3:0] y,
|
||||
|
||||
output [3:0] A,
|
||||
output [3:0] B
|
||||
);
|
||||
|
||||
assign A = x + y;
|
||||
assign B = x - y;
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
read_verilog add_sub.v
|
||||
read_verilog ../common/add_sub.v
|
||||
hierarchy -top top
|
||||
proc
|
||||
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
|
||||
|
|
|
|||
|
|
@ -1,47 +0,0 @@
|
|||
module adff
|
||||
( input d, clk, clr, output reg q );
|
||||
initial begin
|
||||
q = 0;
|
||||
end
|
||||
always @( posedge clk, posedge clr )
|
||||
if ( clr )
|
||||
q <= 1'b0;
|
||||
else
|
||||
q <= d;
|
||||
endmodule
|
||||
|
||||
module adffn
|
||||
( input d, clk, clr, output reg q );
|
||||
initial begin
|
||||
q = 0;
|
||||
end
|
||||
always @( posedge clk, negedge clr )
|
||||
if ( !clr )
|
||||
q <= 1'b0;
|
||||
else
|
||||
q <= d;
|
||||
endmodule
|
||||
|
||||
module dffs
|
||||
( input d, clk, pre, clr, output reg q );
|
||||
initial begin
|
||||
q = 0;
|
||||
end
|
||||
always @( posedge clk )
|
||||
if ( pre )
|
||||
q <= 1'b1;
|
||||
else
|
||||
q <= d;
|
||||
endmodule
|
||||
|
||||
module ndffnr
|
||||
( input d, clk, pre, clr, output reg q );
|
||||
initial begin
|
||||
q = 0;
|
||||
end
|
||||
always @( negedge clk )
|
||||
if ( !clr )
|
||||
q <= 1'b0;
|
||||
else
|
||||
q <= d;
|
||||
endmodule
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
read_verilog adffs.v
|
||||
read_verilog ../common/adffs.v
|
||||
design -save read
|
||||
|
||||
hierarchy -top adff
|
||||
|
|
|
|||
|
|
@ -1,17 +0,0 @@
|
|||
module top (
|
||||
out,
|
||||
clk,
|
||||
reset
|
||||
);
|
||||
output [7:0] out;
|
||||
input clk, reset;
|
||||
reg [7:0] out;
|
||||
|
||||
always @(posedge clk, posedge reset)
|
||||
if (reset) begin
|
||||
out <= 8'b0 ;
|
||||
end else
|
||||
out <= out + 1;
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
read_verilog counter.v
|
||||
read_verilog ../common/counter.v
|
||||
hierarchy -top top
|
||||
proc
|
||||
flatten
|
||||
|
|
|
|||
|
|
@ -1,15 +0,0 @@
|
|||
module dff
|
||||
( input d, clk, output reg q );
|
||||
always @( posedge clk )
|
||||
q <= d;
|
||||
endmodule
|
||||
|
||||
module dffe
|
||||
( input d, clk, en, output reg q );
|
||||
initial begin
|
||||
q = 0;
|
||||
end
|
||||
always @( posedge clk )
|
||||
if ( en )
|
||||
q <= d;
|
||||
endmodule
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
read_verilog dffs.v
|
||||
read_verilog ../common/dffs.v
|
||||
design -save read
|
||||
|
||||
hierarchy -top dff
|
||||
|
|
|
|||
|
|
@ -1,55 +0,0 @@
|
|||
module fsm (
|
||||
clock,
|
||||
reset,
|
||||
req_0,
|
||||
req_1,
|
||||
gnt_0,
|
||||
gnt_1
|
||||
);
|
||||
input clock,reset,req_0,req_1;
|
||||
output gnt_0,gnt_1;
|
||||
wire clock,reset,req_0,req_1;
|
||||
reg gnt_0,gnt_1;
|
||||
|
||||
parameter SIZE = 3 ;
|
||||
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
|
||||
|
||||
reg [SIZE-1:0] state;
|
||||
reg [SIZE-1:0] next_state;
|
||||
|
||||
always @ (posedge clock)
|
||||
begin : FSM
|
||||
if (reset == 1'b1) begin
|
||||
state <= #1 IDLE;
|
||||
gnt_0 <= 0;
|
||||
gnt_1 <= 0;
|
||||
end else
|
||||
case(state)
|
||||
IDLE : if (req_0 == 1'b1) begin
|
||||
state <= #1 GNT0;
|
||||
gnt_0 <= 1;
|
||||
end else if (req_1 == 1'b1) begin
|
||||
gnt_1 <= 1;
|
||||
state <= #1 GNT0;
|
||||
end else begin
|
||||
state <= #1 IDLE;
|
||||
end
|
||||
GNT0 : if (req_0 == 1'b1) begin
|
||||
state <= #1 GNT0;
|
||||
end else begin
|
||||
gnt_0 <= 0;
|
||||
state <= #1 IDLE;
|
||||
end
|
||||
GNT1 : if (req_1 == 1'b1) begin
|
||||
state <= #1 GNT2;
|
||||
gnt_1 <= req_0;
|
||||
end
|
||||
GNT2 : if (req_0 == 1'b1) begin
|
||||
state <= #1 GNT1;
|
||||
gnt_1 <= req_1;
|
||||
end
|
||||
default : state <= #1 IDLE;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
read_verilog fsm.v
|
||||
read_verilog ../common/fsm.v
|
||||
hierarchy -top fsm
|
||||
proc
|
||||
flatten
|
||||
|
|
|
|||
|
|
@ -1,24 +0,0 @@
|
|||
module latchp
|
||||
( input d, clk, en, output reg q );
|
||||
always @*
|
||||
if ( en )
|
||||
q <= d;
|
||||
endmodule
|
||||
|
||||
module latchn
|
||||
( input d, clk, en, output reg q );
|
||||
always @*
|
||||
if ( !en )
|
||||
q <= d;
|
||||
endmodule
|
||||
|
||||
module latchsr
|
||||
( input d, clk, en, clr, pre, output reg q );
|
||||
always @*
|
||||
if ( clr )
|
||||
q <= 1'b0;
|
||||
else if ( pre )
|
||||
q <= 1'b1;
|
||||
else if ( en )
|
||||
q <= d;
|
||||
endmodule
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
read_verilog latches.v
|
||||
read_verilog ../common/latches.v
|
||||
design -save read
|
||||
|
||||
hierarchy -top latchp
|
||||
|
|
|
|||
|
|
@ -1,18 +0,0 @@
|
|||
module top
|
||||
(
|
||||
input [0:7] in,
|
||||
output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
|
||||
);
|
||||
|
||||
assign B1 = in[0] & in[1];
|
||||
assign B2 = in[0] | in[1];
|
||||
assign B3 = in[0] ~& in[1];
|
||||
assign B4 = in[0] ~| in[1];
|
||||
assign B5 = in[0] ^ in[1];
|
||||
assign B6 = in[0] ~^ in[1];
|
||||
assign B7 = ~in[0];
|
||||
assign B8 = in[0];
|
||||
assign B9 = in[0:1] && in [2:3];
|
||||
assign B10 = in[0:1] || in [2:3];
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
read_verilog logic.v
|
||||
read_verilog ../common/logic.v
|
||||
hierarchy -top top
|
||||
proc
|
||||
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
|
||||
|
|
|
|||
|
|
@ -1,11 +0,0 @@
|
|||
module top
|
||||
(
|
||||
input [5:0] x,
|
||||
input [5:0] y,
|
||||
|
||||
output [11:0] A,
|
||||
);
|
||||
|
||||
assign A = x * y;
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
read_verilog mul.v
|
||||
read_verilog ../common/mul.v
|
||||
hierarchy -top top
|
||||
proc
|
||||
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
|
||||
|
|
|
|||
|
|
@ -1,65 +0,0 @@
|
|||
module mux2 (S,A,B,Y);
|
||||
input S;
|
||||
input A,B;
|
||||
output reg Y;
|
||||
|
||||
always @(*)
|
||||
Y = (S)? B : A;
|
||||
endmodule
|
||||
|
||||
module mux4 ( S, D, Y );
|
||||
|
||||
input[1:0] S;
|
||||
input[3:0] D;
|
||||
output Y;
|
||||
|
||||
reg Y;
|
||||
wire[1:0] S;
|
||||
wire[3:0] D;
|
||||
|
||||
always @*
|
||||
begin
|
||||
case( S )
|
||||
0 : Y = D[0];
|
||||
1 : Y = D[1];
|
||||
2 : Y = D[2];
|
||||
3 : Y = D[3];
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module mux8 ( S, D, Y );
|
||||
|
||||
input[2:0] S;
|
||||
input[7:0] D;
|
||||
output Y;
|
||||
|
||||
reg Y;
|
||||
wire[2:0] S;
|
||||
wire[7:0] D;
|
||||
|
||||
always @*
|
||||
begin
|
||||
case( S )
|
||||
0 : Y = D[0];
|
||||
1 : Y = D[1];
|
||||
2 : Y = D[2];
|
||||
3 : Y = D[3];
|
||||
4 : Y = D[4];
|
||||
5 : Y = D[5];
|
||||
6 : Y = D[6];
|
||||
7 : Y = D[7];
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module mux16 (D, S, Y);
|
||||
input [15:0] D;
|
||||
input [3:0] S;
|
||||
output Y;
|
||||
|
||||
assign Y = D[S];
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
read_verilog mux.v
|
||||
read_verilog ../common/mux.v
|
||||
design -save read
|
||||
|
||||
hierarchy -top mux2
|
||||
|
|
|
|||
|
|
@ -1,16 +0,0 @@
|
|||
module top (
|
||||
out,
|
||||
clk,
|
||||
in
|
||||
);
|
||||
output [7:0] out;
|
||||
input signed clk, in;
|
||||
reg signed [7:0] out = 0;
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
out <= out >> 1;
|
||||
out[7] <= in;
|
||||
end
|
||||
|
||||
endmodule
|
||||
Some files were not shown because too many files have changed in this diff Show more
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Add table
Add a link
Reference in a new issue