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fix wide luts
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2 changed files with 22 additions and 19 deletions
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@ -15,33 +15,36 @@ select -assert-none t:LUT3 t:IBUF t:OBUF %% t:* %D
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design -load read
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hierarchy -top mux4
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proc
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equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check
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equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux4 # Constrain all select calls below inside the top module
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select -assert-count 2 t:LUT4
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select -assert-count 4 t:LUT4
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select -assert-count 2 t:MUX2_LUT5
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select -assert-count 1 t:MUX2_LUT6
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select -assert-count 6 t:IBUF
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select -assert-count 1 t:OBUF
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select -assert-none t:LUT4 t:IBUF t:OBUF %% t:* %D
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select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D
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design -load read
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hierarchy -top mux8
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proc
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equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check
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equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux8 # Constrain all select calls below inside the top module
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select -assert-count 11 t:IBUF
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select -assert-count 1 t:OBUF
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select -assert-none t:LUT4 t:IBUF t:OBUF %% t:* %D
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select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D
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design -load read
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hierarchy -top mux16
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proc
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equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check
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equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux16 # Constrain all select calls below inside the top module
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select -assert-count 20 t:IBUF
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select -assert-count 1 t:OBUF
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show
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select -assert-none t:LUT4 t:LUT3 t:IBUF t:OBUF %% t:* %D
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select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:MUX2_LUT6 t:MUX2_LUT7 t:MUX2_LUT8 t:IBUF t:OBUF %% t:* %D
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