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Add testcase

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This commit is contained in:
Eddie Hung 2019-12-13 10:26:30 -08:00
parent 9ab1feeaf1
commit d86d073ad6
1 changed files with 49 additions and 0 deletions
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tests/opt/opt_merge_init.ys Normal file
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read_verilog -icells <<EOT
module top(input clk, i, (* init = 1'b0 *) output o, p);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) ffo (
.CLK(clk),
.D(i),
.Q(o)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) ffp (
.CLK(clk),
.D(i),
.Q(p)
);
endmodule
EOT
opt_merge
select -assert-count 1 a:init=1'0
design -reset
read_verilog -icells <<EOT
module top(input clk, i, (* init = 2'b11 *) output [1:0] o);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) ff1 (
.CLK(clk),
.D(i),
.Q(o[1])
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) ff0 (
.CLK(clk),
.D(i),
.Q(o[0])
);
endmodule
EOT
opt_merge
select -assert-count 1 a:init=2'bx1