abhinavputhran
ec54c36850
dfflibmap: pass selection to dfflegalize dfflibmap was calling dfflegalize on the whole design regardless of the active selection, causing unselected modules to be modified. Fix by appending selected module names to the dfflegalize command. Fixes #5650
2026-03-06 15:13:04 -05:00
KrystalDelusion
1d3f9b7905
Merge pull request #5687 from YosysHQ/nella/pdr-doc
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Update help text for rename -witness and write_aiger -ywmap
2026-03-02 09:29:25 +13:00
Emil J
5f8489d36d
Merge pull request #5666 from YosysHQ/emil/equiv_induct-missing-model-errors
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equiv_induct: error on missing model
2026-02-25 15:39:31 +01:00
Miodrag Milanović
0ed7c5ad53
Merge pull request #5620 from YosysHQ/lofty/abc9-verify
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abc9: verify post-mapping equivalence by default
2026-02-20 13:41:11 +01:00
Krystine Sherwin
094481739f
memory_libmap: Add -force-params
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Reduce complexity for adi brams by unconditionally providing the WIDTH and ABITS parameters.
2026-02-20 10:57:00 +00:00
nella
01e89a8f9e
Remove cell mentions.
2026-02-18 09:29:35 +01:00
nella
2b4f481850
Cleanup docs.
2026-02-18 09:24:41 +01:00
Emil J. Tywoniak
77f64de997
satgen: move report_missing_model here from equiv.h
2026-02-16 17:01:09 +01:00
Emil J. Tywoniak
81ea922512
sat: use the same cell import warnings as equiv
2026-02-16 16:54:26 +01:00
nella
e6e57b33e3
document abc --keep-going pdr [sc-220].
2026-02-15 09:00:04 +01:00
Gus Smith
8ab105ac28
Merge pull request #4303 from Coloquinte/sat_choice
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Infrastructure to run a Sat solver as a command
2026-02-11 06:54:53 -08:00
Emil J
fba29ea8f1
Merge pull request #5679 from YosysHQ/emil/abc9-remove-liberty
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abc9: remove -liberty
2026-02-11 12:36:29 +01:00
Emil J. Tywoniak
915912cc76
abc9: remove -dont_use
2026-02-11 11:39:09 +01:00
Emil J. Tywoniak
c4094e457b
abc9: remove -genlib, -constr
2026-02-11 11:34:54 +01:00
Emil J. Tywoniak
5a46106a46
abc9: remove -liberty
2026-02-11 01:04:50 +01:00
Gus Smith
6f6fa49d3c
Typo
2026-02-09 09:05:56 -08:00
Gus Smith
1502e23371
Set solver from scratchpad or command line
2026-02-06 19:26:32 -08:00
Gus Smith
f062a0c8d6
Typo
2026-02-06 17:26:08 -08:00
Robert O'Callahan
34f8582725
Sanitize ABC global and per-run temporary directory names in logs
2026-02-07 12:12:13 +13:00
Emil J
1717fa0180
Merge pull request #5663 from YosysHQ/emil/opt_expr-fix-pow-shift
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opt_expr: fix const lhs of $pow to $shl
2026-02-05 13:09:01 +01:00
Emil J
8bbde80e02
Merge pull request #5631 from rocallahan/cleanup-compare-signals
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Clean up `compare_signals()` in `opt_clean`
2026-02-04 17:45:05 +01:00
Emil J
992e64342c
Merge pull request #5621 from rocallahan/remove-opt-sort
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Remove `Design::sort()` calls from optimization passes
2026-02-04 16:55:56 +01:00
Robert O'Callahan
7326bb7d66
Only reuse ABC processes if we're using yosys-abc and it was built with ENABLE_READLINE
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(cherry picked from commit 5054fd17d7b70f2df97360bb0f0cc1c92a6ffe72)
2026-02-04 17:19:10 +13:00
Emil J. Tywoniak
ed53ff2f49
equiv_simple, equiv_induct: fix config
2026-02-03 18:37:39 +01:00
Emil J. Tywoniak
8d1c1faf82
equiv_simple, equiv_induct: error by default on missing model, add -ignore-unknown-cells
2026-02-03 18:10:29 +01:00
Emil J. Tywoniak
8e73e2a306
sat: add -ignore-unknown-cells instead of -ignore_unknown_cells for consistency
2026-02-03 18:10:29 +01:00
Emil J. Tywoniak
000be270ca
equiv_simple, equiv_induct: refactor
2026-02-03 17:54:46 +01:00
Emil J. Tywoniak
3bfeaee8ca
opt_expr: fix const lhs of $pow to $shl
2026-02-03 11:59:00 +01:00
KrystalDelusion
414b1b6019
Merge pull request #5651 from rocallahan/abc-error-nonfatal
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Handle ABC nonfatal "Error:" messages
2026-02-03 08:55:05 +13:00
Miodrag Milanović
ac427a79b0
Merge pull request #5644 from nataliakokoromyti/upstream-linux-perf-unistd
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Add unistd header for Linux
2026-01-30 08:17:43 +01:00
Robert O'Callahan
9c56c93632
Add missing newlines to some 'log_error's
2026-01-30 01:52:19 +00:00
Robert O'Callahan
6af1b5b19c
Don't treat ABC 'Error:' output as indicating a fatal error, since these messages aren't necessarily fatal
2026-01-30 01:52:19 +00:00
Emil J
a68fee1115
Merge pull request #5646 from rocallahan/debug-design_equal
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Dump module details when `design_equal` fails
2026-01-29 18:57:24 +01:00
Robert O'Callahan
139c38ecfa
Dump module details when design_equal fails
2026-01-28 18:32:12 +00:00
nella
8f6c4d40e4
Merge pull request #5623 from YosysHQ/nella/opt-dff-rewrite
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opt_dff restructure.
2026-01-28 14:41:40 +01:00
Natalia
6a6e5f0f54
linux_perf: only include unistd on Linux
2026-01-28 03:44:33 -08:00
Natalia
fc2b7c317f
linux_perf: include unistd for POSIX I/O
2026-01-28 03:14:20 -08:00
Emil J
75008b70e5
Merge pull request #5638 from YosysHQ/emil/linux_perf-fix-help
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linux_perf: mark internal, fix help formatting
2026-01-28 11:06:08 +01:00
Krystine Sherwin
8ed7ac04d8
linux_perf.cc: Fix overlength codeblock
2026-01-28 08:17:56 +13:00
Krystine Sherwin
4031310ebb
linux_perf.cc: Use formatted_help
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Gets the codeblock formatting better.
Also fold the on|off into a single usage.
2026-01-28 08:10:31 +13:00
Gus Smith
09ceadfde7
Merge pull request #4269 from povik/icells_not_derived
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Avoid `module_not_derived` on internal cells in techmap result
2026-01-26 14:48:40 -08:00
Emil J. Tywoniak
ef3b2b0380
linux_perf: mark internal, fix help formatting
2026-01-26 22:59:20 +01:00
nella
9367090763
OptDff more accurate ctrl/pattern desc.
2026-01-26 22:19:36 +01:00
nella
5803461c24
opt_dff pattern extraction.
2026-01-26 22:10:10 +01:00
Emil J
29a9e42b64
Merge pull request #5628 from rocallahan/linux-perf-ctl
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Add `linux_perf` command to turn Linux perf recording on and off.
2026-01-26 19:32:55 +01:00
nella
8576055dea
Fix tests.
2026-01-26 18:41:41 +01:00
Emil J
673c8d1ae7
Merge pull request #5615 from rocallahan/remove-used-signals-updates
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Don't update `used_signals` for retained wires in `rmunused_module_signals`.
2026-01-26 15:47:25 +01:00
nella
a75e0b2e92
opt_dff minor cleanup, added tests for comp var.
2026-01-26 14:24:01 +01:00
Robert O'Callahan
32e96605d4
Don't update used_signals for retained wires in rmunused_module_signals.
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These updates should not be necessary. In fact, if they were necessary, this code
would be buggy, because the results would depend on the order in which wires are traversed:
If wire A is retained, which causes an update to `used_signals`, which then causes wire B
to be retained when it otherwise wouldn't be, then we would get different results depending
on whether A is visited before B.
These updates will also make it difficult to process these wires in parallel.
2026-01-24 03:41:18 +00:00
Robert O'Callahan
7d53d64a47
Make the call to compare_signals() easier to read.
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The negation here is confusing. The intent of the code is "if `s1` is preferred
over `s2` as the canonical `SigBit` for this signal, make `s1` the canonical `SigBit`
in `assign_map`", so write the code that way instead of "if `s2` is not preferred
over `s1` ...".
This doesn't change any behavior now that `compare_signals()` is a total order,
i.e. `s1` is preferred over `s2`, `s2` is preferred over `s1`, or `s1` and `s2` are equal.
Now, when `s1` and `s2` are equal, we don't call `assign_map.add(s1)`, but that's
already a noop in that case.
2026-01-24 02:01:05 +00:00
