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document abc --keep-going pdr [sc-220].
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3 changed files with 46 additions and 6 deletions
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@ -931,6 +931,11 @@ struct AigerBackend : public Backend {
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log("\n");
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log(" -ywmap <filename>\n");
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log(" write a map file for conversion to and from yosys witness traces.\n");
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log(" The generated JSON map includes \"asserts\" and \"assumes\" arrays\n");
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log(" containing the hierarchical witness paths of the corresponding\n");
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log(" $assert and $assume cells. This enables downstream tools to map\n");
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log(" AIGER bad-state properties and invariant constraints back to\n");
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log(" individual formal properties by name.\n");
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log("\n");
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log(" -I, -O, -B, -L\n");
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log(" If the design contains no input/output/assert/flip-flop then create one\n");
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@ -3,9 +3,9 @@ Symbolic model checking
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.. todo:: check text context
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.. note::
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While it is possible to perform model checking directly in Yosys, it
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.. note::
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While it is possible to perform model checking directly in Yosys, it
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is highly recommended to use SBY or EQY for formal hardware verification.
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Symbolic Model Checking (SMC) is used to formally prove that a circuit has (or
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@ -117,3 +117,33 @@ Result with fixed :file:`axis_master.v`:
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Solving problem with 159144 variables and 441626 clauses..
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SAT proof finished - no model found: SUCCESS!
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Witness framework and per-property tracking
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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When using AIGER-based formal verification flows (such as the ``abc`` engine in
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SymbiYosys), Yosys provides infrastructure for tracking individual formal
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properties through the verification pipeline.
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The ``rename -witness`` pass (run automatically by ``prep``) assigns public
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names to all cells that participate in the witness framework:
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- Witness signal cells: ``$anyconst``, ``$anyseq``, ``$anyinit``,
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``$allconst``, ``$allseq``
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- Formal property cells: ``$assert``, ``$assume``, ``$cover``, ``$live``,
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``$fair``, ``$check``
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These public names allow downstream tools to refer to individual properties by
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their hierarchical path rather than by anonymous internal identifiers.
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The ``write_aiger -ywmap`` option generates a JSON map file that includes, among
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other things, ``"asserts"`` and ``"assumes"`` arrays. Each entry contains the
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hierarchical witness path of the corresponding ``$assert`` or ``$assume`` cell.
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This lets tools such as SymbiYosys map AIGER bad-state properties and invariant
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constraints back to individual formal properties, enabling features like
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per-property pass/fail reporting (e.g. ``abc pdr`` with ``--keep-going`` mode).
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The ``write_smt2`` backend similarly uses the public witness names when emitting
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``yosys-smt2-assert`` and ``yosys-smt2-assume`` comments. Cells whose
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``hdlname`` attribute contains the ``_witness_`` marker are treated as having
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private names for comment purposes, keeping solver output clean.
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@ -263,9 +263,14 @@ struct RenamePass : public Pass {
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log(" rename -witness\n");
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log("\n");
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log("Assigns auto-generated names to all $any*/$all* output wires and containing\n");
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log("cells that do not have a public name. This ensures that, during formal\n");
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log("verification, a solver-found trace can be fully specified using a public\n");
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log("hierarchical names.\n");
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log("cells that do not have a public name. Also renames formal property cells\n");
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log("($assert, $assume, $cover, $live, $fair, $check) that have private names,\n");
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log("giving them public witness-trackable names.\n");
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log("\n");
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log("This ensures that, during formal verification, a solver-found trace can be\n");
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log("fully specified using public hierarchical names, and that individual property\n");
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log("results can be tracked by name in flows that support per-property reporting\n");
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log("(e.g. SBY with abc pdr in --keep-going mode).\n");
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log("\n");
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log("\n");
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log(" rename -hide [selection]\n");
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