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yosys/passes
Robert O'Callahan 32e96605d4 Don't update used_signals for retained wires in rmunused_module_signals.
These updates should not be necessary. In fact, if they were necessary, this code
would be buggy, because the results would depend on the order in which wires are traversed:
If wire A is retained, which causes an update to `used_signals`, which then causes wire B
to be retained when it otherwise wouldn't be, then we would get different results depending
on whether A is visited before B.

These updates will also make it difficult to process these wires in parallel.
2026-01-24 03:41:18 +00:00
..
cmds Add -on/-off modes to debug pass 2026-01-15 12:07:26 -08:00
equiv Merge pull request #5357 from rocallahan/builtin-ff 2025-09-17 11:37:16 +02:00
fsm fsm_detect: add adff detection 2025-11-06 23:29:47 +02:00
hierarchy hierarchy.cc: Tidying 2025-10-15 09:42:47 +13:00
memory Remove .c_str() from parameters to log_debug() 2025-09-23 19:10:33 +12:00
opt Don't update used_signals for retained wires in rmunused_module_signals. 2026-01-24 03:41:18 +00:00
pmgen Remove .c_str() from log_cmd_error() and log_file_error() parameters 2025-09-16 22:59:08 +00:00
proc proc_clean: Removing an empty full_case is doing something 2026-01-07 13:10:32 +13:00
sat sim.cc: Check eval err 2025-12-15 12:08:07 +13:00
techmap Merge pull request #5593 from RCoeurjoly/RCoeurjoly/5574_fix 2026-01-23 07:16:48 +13:00
tests test_cell.cc: Generate .aag for all compatible cells 2025-12-02 14:03:36 +13:00