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yosys/passes
Robert O'Callahan 7d53d64a47 Make the call to compare_signals() easier to read.
The negation here is confusing. The intent of the code is "if `s1` is preferred
over `s2` as the canonical `SigBit` for this signal, make `s1` the canonical `SigBit`
in `assign_map`", so write the code that way instead of "if `s2` is not preferred
over `s1` ...".

This doesn't change any behavior now that `compare_signals()` is a total order,
i.e. `s1` is preferred over `s2`, `s2` is preferred over `s1`, or `s1` and `s2` are equal.
Now, when `s1` and `s2` are equal, we don't call `assign_map.add(s1)`, but that's
already a noop in that case.
2026-01-24 02:01:05 +00:00
..
cmds Add -on/-off modes to debug pass 2026-01-15 12:07:26 -08:00
equiv Merge pull request #5357 from rocallahan/builtin-ff 2025-09-17 11:37:16 +02:00
fsm fsm_detect: add adff detection 2025-11-06 23:29:47 +02:00
hierarchy hierarchy.cc: Tidying 2025-10-15 09:42:47 +13:00
memory Remove .c_str() from parameters to log_debug() 2025-09-23 19:10:33 +12:00
opt Make the call to compare_signals() easier to read. 2026-01-24 02:01:05 +00:00
pmgen Remove .c_str() from log_cmd_error() and log_file_error() parameters 2025-09-16 22:59:08 +00:00
proc proc_clean: Removing an empty full_case is doing something 2026-01-07 13:10:32 +13:00
sat sim.cc: Check eval err 2025-12-15 12:08:07 +13:00
techmap Merge pull request #5593 from RCoeurjoly/RCoeurjoly/5574_fix 2026-01-23 07:16:48 +13:00
tests test_cell.cc: Generate .aag for all compatible cells 2025-12-02 14:03:36 +13:00