abhinavputhran ec54c36850 dfflibmap: pass selection to dfflegalize dfflibmap was calling dfflegalize on the whole design regardless of the active selection, causing unselected modules to be modified. Fix by appending selected module names to the dfflegalize command. Fixes #5650		2026-03-06 15:13:04 -05:00
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cmds	Merge pull request #5687 from YosysHQ/nella/pdr-doc	2026-03-02 09:29:25 +13:00
equiv	satgen: move report_missing_model here from equiv.h	2026-02-16 17:01:09 +01:00
fsm	fsm_detect: add adff detection	2025-11-06 23:29:47 +02:00
hierarchy	hierarchy.cc: Tidying	2025-10-15 09:42:47 +13:00
memory	memory_libmap: Add -force-params	2026-02-20 10:57:00 +00:00
opt	Merge pull request #5663 from YosysHQ/emil/opt_expr-fix-pow-shift	2026-02-05 13:09:01 +01:00
pmgen	Remove .c_str() from log_cmd_error() and log_file_error() parameters	2025-09-16 22:59:08 +00:00
proc	proc_clean: Removing an empty full_case is doing something	2026-01-07 13:10:32 +13:00
sat	Merge pull request #5666 from YosysHQ/emil/equiv_induct-missing-model-errors	2026-02-25 15:39:31 +01:00
techmap	dfflibmap: pass selection to dfflegalize dfflibmap was calling dfflegalize on the whole design regardless of the active selection, causing unselected modules to be modified. Fix by appending selected module names to the dfflegalize command. Fixes #5650	2026-03-06 15:13:04 -05:00
tests	test_cell.cc: Generate .aag for all compatible cells	2025-12-02 14:03:36 +13:00