1871 commits

Author	SHA1	Message	Date
Miodrag Milanovic	7e4aef06e4	Add register file mapping	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	41ae513d60	support other I/O configurations	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	34f08bc639	Enable nanoxplore tests	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	a5bfb23b47	start cleaning rams	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	65d2ebac9d	fix test	2024-08-15 17:50:36 +02:00
Lofty	b0c4add642	Added lutram	2024-08-15 17:50:36 +02:00
Lofty	b3f59c9820	Add NX_CY	2024-08-15 17:50:36 +02:00
Lofty	b4e9bb0d85	Add FFs and related tests	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	b4a17cccc3	add few more tests	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	93543bd874	add lut tests	2024-08-15 17:50:36 +02:00
Akash Levy	34e5bc1129	Merge branch 'YosysHQ:main' into master	2024-08-14 16:56:53 -07:00
Martin Povišer	c35f5e379c	Extend liberty tests	2024-08-13 18:47:36 +02:00
Akash Levy	c0af4604bc	Update Yosys	2024-07-30 16:55:18 -07:00
N. Engelhardt	9f869b265c	Merge pull request #4474 from tony-min-1/mchp ... Add PolarFire FPGA support	2024-07-29 15:28:44 +02:00
Emil J. Tywoniak	01fd72520f	proc_rom: test src attribute on memories	2024-07-29 10:13:45 +02:00
chunlin min	3db69b7a10	inline all tests. Add switch to remove init values as PolarFire DFFs do not support init	2024-07-08 17:03:03 -04:00
Tony Min	d41688f7d7	Revisions (#4) ... * area should be 1 for all LUTs * clean up macros * add log_assert to fail noisily when encountering oddly configured DFF * clean help msg * flatten set to true by default * update * merge mult tests * remove redundant test * move all dsp tests to single file and remove redundant tests * update ram tests * add more dff tests * fix c++20 compile errors * add option to dump verilog * default to use abc9 * remove -abc9 option since its the default now --------- Co-authored-by: tony <minchunlin@gmail.com>	2024-07-08 10:57:16 -04:00
Tony Min	6fe0e00050	Add missing u sram init (#3) ... add missing INIT for uSRAM	2024-07-04 16:39:10 -04:00
chunlin min	8e7ec2d660	add assertions for synth_microchip tests	2024-07-04 15:45:44 -04:00
chunlin min	e3c4791e5b	move microchip tests from techlibs/microchip/tests to tests/arch/microchip	2024-07-04 14:16:52 -04:00
Akash Levy	e23e33441f	Update yosys from upstream	2024-06-15 14:23:24 -07:00
phsauter	34b5c6d062	peepopt: avoid shift-amount underflow	2024-06-13 23:30:07 +02:00
Marian Buschsieweke	7f89a45ad7	cxxxrtl: fix use of format specifiers in test ... This fix a few instances of incorrect (and non-portable) use of format specifiers.	2024-06-11 07:22:39 +01:00
Asherah Connor	dc69365258	cxxrtl: failing test: unconnected blackbox outputs don't compile.	2024-06-07 14:24:27 +03:00
Akash Levy	e0d96d35a1	Merge branch 'YosysHQ:main' into master	2024-06-01 23:47:26 -07:00
Martin Povišer	4b67f3757f	Merge pull request #4404 from YosysHQ/povik/bbox_derive ... box_derive: New command to derive modules for boxes	2024-05-31 19:09:18 +02:00
Martin Povišer	97fedff383	box_derive: Tune the test	2024-05-29 20:42:11 +02:00
Akash Levy	5173e329ea	Sync yosys	2024-05-21 19:07:13 -07:00
Martin Povišer	bff2443af8	box_derive: Finish the test	2024-05-21 16:34:49 +02:00
Martin Povišer	c0a196173a	Rename bbox_derive to box_derive	2024-05-21 16:18:03 +02:00
N. Engelhardt	24f9329c67	Merge pull request #4367 from YosysHQ/lofty/intel_alm-drop-quartus ... intel_alm: drop quartus support	2024-05-21 16:01:23 +02:00
Martin Povišer	557db4ea46	bbox_drive: Add an incomplete test	2024-05-21 14:57:49 +02:00
Akash Levy	0e77a03359	Merge branch 'YosysHQ:main' into master	2024-05-06 21:11:06 -07:00
Martin Povišer	b143e5678f	cellmatch: Rename the special design to $cellmatch	2024-05-03 16:42:41 +02:00
Martin Povišer	913bc87c44	cellmatch: Add test	2024-05-03 16:42:41 +02:00
Emil J. Tywoniak	a833f05036	techmap: add dynamic cell type test	2024-05-03 13:53:49 +02:00
Lofty	8cc9aa7fc6	intel_alm: drop quartus support	2024-05-03 11:32:33 +01:00
Akash Levy	8c330c0e4b	Merge branch 'YosysHQ:main' into master	2024-04-29 22:22:47 -07:00
George Rennie	4e6deb53b6	read_aiger: Fix incorrect read of binary Aiger without outputs ... * Also makes all ascii parsing finish reading lines and adds a small test	2024-04-29 14:06:58 +01:00
Akash Levy	45b723d6f3	Merge branch 'YosysHQ:main' into master	2024-04-25 06:24:57 -07:00
Akash Levy	6a3bb58d5d	Updates from yosys	2024-04-14 18:53:44 -07:00
N. Engelhardt	e8ec19c273	add command that should not have any effect to hierarchy -generate test (this documents the current behavior, not sure if it is desired functionality)	2024-04-12 13:51:06 +02:00
N. Engelhardt	b87327d1b9	fix hierarchy -generate mode handling of cells	2024-04-12 13:38:33 +02:00
Miodrag Milanovic	0c7ac36dcf	Add workflows and CODEOWNERS and fixed gitignore	2024-04-11 14:56:00 +02:00
Akash Levy	29e9d3ea92	Updates for hiding verific	2024-04-09 07:16:22 -07:00
Akash Levy	e3f633fae6	Merge branch 'YosysHQ:main' into master	2024-04-08 12:26:40 -07:00
Martin Povišer	dc746080f5	Merge pull request #4298 from povik/kogge-stone ... techmap: Add a Kogge-Stone option for `$lcu` mapping	2024-04-08 16:46:06 +02:00
N. Engelhardt	8e8885e1cc	Merge pull request #4323 from YosysHQ/tests_update ... Tests update for latest more strict iverilog	2024-04-08 15:10:59 +02:00
Miodrag Milanovic	4ac10040ce	Enable SV for localparam use by Efinix cell_sim	2024-04-08 12:45:43 +02:00
Miodrag Milanovic	91e41d8c80	Move parameters to module declaration	2024-04-08 12:44:37 +02:00